prev_cmp_rs_ccd.tan.qmsg

基于CPLD的CCD驱动程序源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "ACLK register lpm_counter:Address3_rtl_1\|dffs\[1\] register lpm_counter:Address3_rtl_1\|dffs\[17\] 81.97 MHz 12.2 ns Internal " "Info: Clock \"ACLK\" has Internal fmax of 81.97 MHz between source register \"lpm_counter:Address3_rtl_1\|dffs\[1\]\" and destination register \"lpm_counter:Address3_rtl_1\|dffs\[17\]\" (period= 12.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register register " "Info: + Longest register to register delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Address3_rtl_1\|dffs\[1\] 1 REG LC130 61 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC130; Fanout = 61; REG Node = 'lpm_counter:Address3_rtl_1\|dffs\[1\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:Address3_rtl_1|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.300 ns) 5.000 ns lpm_counter:Address3_rtl_1\|dffs\[17\]~727 2 COMB LC226 1 " "Info: 2: + IC(3.700 ns) + CELL(1.300 ns) = 5.000 ns; Loc. = LC226; Fanout = 1; COMB Node = 'lpm_counter:Address3_rtl_1\|dffs\[17\]~727'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { lpm_counter:Address3_rtl_1|dffs[1] lpm_counter:Address3_rtl_1|dffs[17]~727 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 5.600 ns lpm_counter:Address3_rtl_1\|dffs\[17\]~733 3 COMB LC227 1 " "Info: 3: + IC(0.000 ns) + CELL(0.600 ns) = 5.600 ns; Loc. = LC227; Fanout = 1; COMB Node = 'lpm_counter:Address3_rtl_1\|dffs\[17\]~733'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { lpm_counter:Address3_rtl_1|dffs[17]~727 lpm_counter:Address3_rtl_1|dffs[17]~733 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 7.700 ns lpm_counter:Address3_rtl_1\|dffs\[17\] 4 REG LC228 101 " "Info: 4: + IC(0.000 ns) + CELL(2.100 ns) = 7.700 ns; Loc. = LC228; Fanout = 101; REG Node = 'lpm_counter:Address3_rtl_1\|dffs\[17\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lpm_counter:Address3_rtl_1|dffs[17]~733 lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 51.95 % ) " "Info: Total cell delay = 4.000 ns ( 51.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 48.05 % ) " "Info: Total interconnect delay = 3.700 ns ( 48.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { lpm_counter:Address3_rtl_1|dffs[1] lpm_counter:Address3_rtl_1|dffs[17]~727 lpm_counter:Address3_rtl_1|dffs[17]~733 lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "7.700 ns" { lpm_counter:Address3_rtl_1|dffs[1] {} lpm_counter:Address3_rtl_1|dffs[17]~727 {} lpm_counter:Address3_rtl_1|dffs[17]~733 {} lpm_counter:Address3_rtl_1|dffs[17] {} } { 0.000ns 3.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.600ns 2.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ACLK destination 6.900 ns + Shortest register " "Info: + Shortest clock path from clock \"ACLK\" to destination register is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns ACLK 1 CLK PIN_98 18 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_98; Fanout = 18; CLK Node = 'ACLK'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ACLK } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.100 ns) 6.900 ns lpm_counter:Address3_rtl_1\|dffs\[17\] 2 REG LC228 101 " "Info: 2: + IC(3.600 ns) + CELL(2.100 ns) = 6.900 ns; Loc. = LC228; Fanout = 101; REG Node = 'lpm_counter:Address3_rtl_1\|dffs\[17\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns ( 47.83 % ) " "Info: Total cell delay = 3.300 ns ( 47.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 52.17 % ) " "Info: Total interconnect delay = 3.600 ns ( 52.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { ACLK {} ACLK~out {} lpm_counter:Address3_rtl_1|dffs[17] {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 1.200ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ACLK source 6.900 ns - Longest register " "Info: - Longest clock path from clock \"ACLK\" to source register is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns ACLK 1 CLK PIN_98 18 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_98; Fanout = 18; CLK Node = 'ACLK'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ACLK } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.100 ns) 6.900 ns lpm_counter:Address3_rtl_1\|dffs\[1\] 2 REG LC130 61 " "Info: 2: + IC(3.600 ns) + CELL(2.100 ns) = 6.900 ns; Loc. = LC130; Fanout = 61; REG Node = 'lpm_counter:Address3_rtl_1\|dffs\[1\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[1] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns ( 47.83 % ) " "Info: Total cell delay = 3.300 ns ( 47.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 52.17 % ) " "Info: Total interconnect delay = 3.600 ns ( 52.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[1] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { ACLK {} ACLK~out {} lpm_counter:Address3_rtl_1|dffs[1] {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 1.200ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { ACLK {} ACLK~out {} lpm_counter:Address3_rtl_1|dffs[17] {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 1.200ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[1] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { ACLK {} ACLK~out {} lpm_counter:Address3_rtl_1|dffs[1] {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 1.200ns 2.100ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { lpm_counter:Address3_rtl_1|dffs[1] lpm_counter:Address3_rtl_1|dffs[17]~727 lpm_counter:Address3_rtl_1|dffs[17]~733 lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "7.700 ns" { lpm_counter:Address3_rtl_1|dffs[1] {} lpm_counter:Address3_rtl_1|dffs[17]~727 {} lpm_counter:Address3_rtl_1|dffs[17]~733 {} lpm_counter:Address3_rtl_1|dffs[17] {} } { 0.000ns 3.700ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.600ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[17] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { ACLK {} ACLK~out {} lpm_counter:Address3_rtl_1|dffs[17] {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 1.200ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { ACLK lpm_counter:Address3_rtl_1|dffs[1] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { ACLK {} ACLK~out {} lpm_counter:Address3_rtl_1|dffs[1] {} } { 0.000ns 0.000ns 3.600ns } { 0.000ns 1.200ns 2.100ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:Address2_rtl_2\|dffs\[10\] START CLK 2.200 ns register " "Info: tsu for register \"lpm_counter:Address2_rtl_2\|dffs\[10\]\" (data pin = \"START\", clock pin = \"CLK\") is 2.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.200 ns + Longest pin register " "Info: + Longest pin to register delay is 17.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns START 1 PIN PIN_102 83 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_102; Fanout = 83; PIN Node = 'START'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.300 ns) 9.500 ns CS~18 2 COMB LOOP LC166 126 " "Info: 2: + IC(0.000 ns) + CELL(8.300 ns) = 9.500 ns; Loc. = LC166; Fanout = 126; COMB LOOP Node = 'CS~18'" { { "Info" "ITDB_PART_OF_SCC" "CS~18 LC166 " "Info: Loc. = LC166; Node \"CS~18\"" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS~18 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS~18 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 19 -1 0 } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { START CS~18 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.300 ns) 14.500 ns lpm_counter:Address2_rtl_2\|dffs\[10\]~807 3 COMB LC45 1 " "Info: 3: + IC(3.700 ns) + CELL(1.300 ns) = 14.500 ns; Loc. = LC45; Fanout = 1; COMB Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]~807'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { CS~18 lpm_counter:Address2_rtl_2|dffs[10]~807 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 15.100 ns lpm_counter:Address2_rtl_2\|dffs\[10\]~812 4 COMB LC46 1 " "Info: 4: + IC(0.000 ns) + CELL(0.600 ns) = 15.100 ns; Loc. = LC46; Fanout = 1; COMB Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]~812'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { lpm_counter:Address2_rtl_2|dffs[10]~807 lpm_counter:Address2_rtl_2|dffs[10]~812 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 17.200 ns lpm_counter:Address2_rtl_2\|dffs\[10\] 5 REG LC47 62 " "Info: 5: + IC(0.000 ns) + CELL(2.100 ns) = 17.200 ns; Loc. = LC47; Fanout = 62; REG Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lpm_counter:Address2_rtl_2|dffs[10]~812 lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.500 ns ( 78.49 % ) " "Info: Total cell delay = 13.500 ns ( 78.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 21.51 % ) " "Info: Total interconnect delay = 3.700 ns ( 21.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.200 ns" { START CS~18 lpm_counter:Address2_rtl_2|dffs[10]~807 lpm_counter:Address2_rtl_2|dffs[10]~812 lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.200 ns" { START {} START~out {} CS~18 {} lpm_counter:Address2_rtl_2|dffs[10]~807 {} lpm_counter:Address2_rtl_2|dffs[10]~812 {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.700ns 0.000ns 0.000ns } { 0.000ns 1.200ns 8.300ns 1.300ns 0.600ns 2.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 17.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 17.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns CLK 1 CLK PIN_184 6 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_184; Fanout = 6; CLK Node = 'CLK'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns num1\[2\] 2 REG LC17 2 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC17; Fanout = 2; REG Node = 'num1\[2\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK num1[2] } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 12.000 ns Equal0~13sexpbal 3 COMB LC22 29 " "Info: 3: + IC(3.200 ns) + CELL(4.000 ns) = 12.000 ns; Loc. = LC22; Fanout = 29; COMB Node = 'Equal0~13sexpbal'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { num1[2] Equal0~13sexpbal } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.100 ns) 17.900 ns lpm_counter:Address2_rtl_2\|dffs\[10\] 4 REG LC47 62 " "Info: 4: + IC(3.800 ns) + CELL(2.100 ns) = 17.900 ns; Loc. = LC47; Fanout = 62; REG Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { Equal0~13sexpbal lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.900 ns ( 60.89 % ) " "Info: Total cell delay = 10.900 ns ( 60.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 39.11 % ) " "Info: Total interconnect delay = 7.000 ns ( 39.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.900 ns" { CLK num1[2] Equal0~13sexpbal lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.900 ns" { CLK {} CLK~out {} num1[2] {} Equal0~13sexpbal {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.200ns 3.800ns } { 0.000ns 2.400ns 2.400ns 4.000ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.200 ns" { START CS~18 lpm_counter:Address2_rtl_2|dffs[10]~807 lpm_counter:Address2_rtl_2|dffs[10]~812 lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.200 ns" { START {} START~out {} CS~18 {} lpm_counter:Address2_rtl_2|dffs[10]~807 {} lpm_counter:Address2_rtl_2|dffs[10]~812 {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.700ns 0.000ns 0.000ns } { 0.000ns 1.200ns 8.300ns 1.300ns 0.600ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.900 ns" { CLK num1[2] Equal0~13sexpbal lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.900 ns" { CLK {} CLK~out {} num1[2] {} Equal0~13sexpbal {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.200ns 3.800ns } { 0.000ns 2.400ns 2.400ns 4.000ns 2.100ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK JSUB lpm_counter:NumVH_rtl_3\|dffs\[0\] 47.500 ns register " "Info: tco from clock \"CLK\" to destination pin \"JSUB\" through register \"lpm_counter:NumVH_rtl_3\|dffs\[0\]\" is 47.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 25.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 25.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns CLK 1 CLK PIN_184 6 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_184; Fanout = 6; CLK Node = 'CLK'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns num1\[0\] 2 REG LC231 4 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC231; Fanout = 4; REG Node = 'num1\[0\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK num1[0] } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 12.100 ns Equal0~13sexpbal 3 COMB LC22 29 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 12.100 ns; Loc. = LC22; Fanout = 29; COMB Node = 'Equal0~13sexpbal'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { num1[0] Equal0~13sexpbal } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(3.700 ns) 19.600 ns lpm_counter:NumRG_rtl_0\|dffs\[6\] 4 REG LC127 103 " "Info: 4: + IC(3.800 ns) + CELL(3.700 ns) = 19.600 ns; Loc. = LC127; Fanout = 103; REG Node = 'lpm_counter:NumRG_rtl_0\|dffs\[6\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { Equal0~13sexpbal lpm_counter:NumRG_rtl_0|dffs[6] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.100 ns) 25.400 ns lpm_counter:NumVH_rtl_3\|dffs\[0\] 5 REG LC252 53 " "Info: 5: + IC(3.700 ns) + CELL(2.100 ns) = 25.400 ns; Loc. = LC252; Fanout = 53; REG Node = 'lpm_counter:NumVH_rtl_3\|dffs\[0\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { lpm_counter:NumRG_rtl_0|dffs[6] lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.600 ns ( 57.48 % ) " "Info: Total cell delay = 14.600 ns ( 57.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.800 ns ( 42.52 % ) " "Info: Total interconnect delay = 10.800 ns ( 42.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "25.400 ns" { CLK num1[0] Equal0~13sexpbal lpm_counter:NumRG_rtl_0|dffs[6] lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "25.400 ns" { CLK {} CLK~out {} num1[0] {} Equal0~13sexpbal {} lpm_counter:NumRG_rtl_0|dffs[6] {} lpm_counter:NumVH_rtl_3|dffs[0] {} } { 0.000ns 0.000ns 0.000ns 3.300ns 3.800ns 3.700ns } { 0.000ns 2.400ns 2.400ns 4.000ns 3.700ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.500 ns + Longest register pin " "Info: + Longest register to pin delay is 20.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:NumVH_rtl_3\|dffs\[0\] 1 REG LC252 53 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC252; Fanout = 53; REG Node = 'lpm_counter:NumVH_rtl_3\|dffs\[0\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(3.700 ns) 7.700 ns Equal9~24 2 COMB SEXP181 2 " "Info: 2: + IC(4.000 ns) + CELL(3.700 ns) = 7.700 ns; Loc. = SEXP181; Fanout = 2; COMB Node = 'Equal9~24'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { lpm_counter:NumVH_rtl_3|dffs[0] Equal9~24 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 200 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 11.700 ns SUB~411 3 COMB LC186 5 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 11.700 ns; Loc. = LC186; Fanout = 5; COMB Node = 'SUB~411'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Equal9~24 SUB~411 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.200 ns) 18.900 ns SUB~446 4 COMB LOOP LC253 3 " "Info: 4: + IC(0.000 ns) + CELL(7.200 ns) = 18.900 ns; Loc. = LC253; Fanout = 3; COMB LOOP Node = 'SUB~446'" { { "Info" "ITDB_PART_OF_SCC" "SUB~446 LC253 " "Info: Loc. = LC253; Node \"SUB~446\"" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SUB~446 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { SUB~446 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 20 -1 0 } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { SUB~411 SUB~446 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 20.500 ns JSUB 5 PIN PIN_57 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 20.500 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'JSUB'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { SUB~446 JSUB } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.500 ns ( 80.49 % ) " "Info: Total cell delay = 16.500 ns ( 80.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.51 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] Equal9~24 SUB~411 SUB~446 JSUB } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] {} Equal9~24 {} SUB~411 {} SUB~446 {} JSUB {} } { 0.000ns 4.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.700ns 4.000ns 7.200ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "25.400 ns" { CLK num1[0] Equal0~13sexpbal lpm_counter:NumRG_rtl_0|dffs[6] lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "25.400 ns" { CLK {} CLK~out {} num1[0] {} Equal0~13sexpbal {} lpm_counter:NumRG_rtl_0|dffs[6] {} lpm_counter:NumVH_rtl_3|dffs[0] {} } { 0.000ns 0.000ns 0.000ns 3.300ns 3.800ns 3.700ns } { 0.000ns 2.400ns 2.400ns 4.000ns 3.700ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] Equal9~24 SUB~411 SUB~446 JSUB } "NODE_NAME" } } { "e:/program files/quartus2/qu