rs_ccd.tan.qmsg

基于CPLD的CCD驱动程序源码

{ "Info" "ITDB_TSU_RESULT" "lpm_counter:Address2_rtl_2\|dffs\[10\] START CLK 2.400 ns register " "Info: tsu for register \"lpm_counter:Address2_rtl_2\|dffs\[10\]\" (data pin = \"START\", clock pin = \"CLK\") is 2.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.400 ns + Longest pin register " "Info: + Longest pin to register delay is 17.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns START 1 PIN PIN_102 83 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_102; Fanout = 83; PIN Node = 'START'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.400 ns) 9.600 ns CS~18 2 COMB LOOP LC214 126 " "Info: 2: + IC(0.000 ns) + CELL(8.400 ns) = 9.600 ns; Loc. = LC214; Fanout = 126; COMB LOOP Node = 'CS~18'" { { "Info" "ITDB_PART_OF_SCC" "CS~18 LC214 " "Info: Loc. = LC214; Node \"CS~18\"" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS~18 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS~18 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 19 -1 0 } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.400 ns" { START CS~18 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.300 ns) 14.700 ns lpm_counter:Address2_rtl_2\|dffs\[10\]~807 3 COMB LC161 1 " "Info: 3: + IC(3.800 ns) + CELL(1.300 ns) = 14.700 ns; Loc. = LC161; Fanout = 1; COMB Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]~807'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { CS~18 lpm_counter:Address2_rtl_2|dffs[10]~807 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 15.300 ns lpm_counter:Address2_rtl_2\|dffs\[10\]~812 4 COMB LC162 1 " "Info: 4: + IC(0.000 ns) + CELL(0.600 ns) = 15.300 ns; Loc. = LC162; Fanout = 1; COMB Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]~812'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { lpm_counter:Address2_rtl_2|dffs[10]~807 lpm_counter:Address2_rtl_2|dffs[10]~812 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 17.400 ns lpm_counter:Address2_rtl_2\|dffs\[10\] 5 REG LC163 62 " "Info: 5: + IC(0.000 ns) + CELL(2.100 ns) = 17.400 ns; Loc. = LC163; Fanout = 62; REG Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lpm_counter:Address2_rtl_2|dffs[10]~812 lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns ( 78.16 % ) " "Info: Total cell delay = 13.600 ns ( 78.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 21.84 % ) " "Info: Total interconnect delay = 3.800 ns ( 21.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.400 ns" { START CS~18 lpm_counter:Address2_rtl_2|dffs[10]~807 lpm_counter:Address2_rtl_2|dffs[10]~812 lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.400 ns" { START {} START~out {} CS~18 {} lpm_counter:Address2_rtl_2|dffs[10]~807 {} lpm_counter:Address2_rtl_2|dffs[10]~812 {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.800ns 0.000ns 0.000ns } { 0.000ns 1.200ns 8.400ns 1.300ns 0.600ns 2.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 17.900 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 17.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns CLK 1 CLK PIN_184 6 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_184; Fanout = 6; CLK Node = 'CLK'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns num1\[2\] 2 REG LC87 2 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC87; Fanout = 2; REG Node = 'num1\[2\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK num1[2] } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 12.000 ns Equal0~13sexpbal 3 COMB LC85 29 " "Info: 3: + IC(3.200 ns) + CELL(4.000 ns) = 12.000 ns; Loc. = LC85; Fanout = 29; COMB Node = 'Equal0~13sexpbal'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { num1[2] Equal0~13sexpbal } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.100 ns) 17.900 ns lpm_counter:Address2_rtl_2\|dffs\[10\] 4 REG LC163 62 " "Info: 4: + IC(3.800 ns) + CELL(2.100 ns) = 17.900 ns; Loc. = LC163; Fanout = 62; REG Node = 'lpm_counter:Address2_rtl_2\|dffs\[10\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { Equal0~13sexpbal lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.900 ns ( 60.89 % ) " "Info: Total cell delay = 10.900 ns ( 60.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 39.11 % ) " "Info: Total interconnect delay = 7.000 ns ( 39.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.900 ns" { CLK num1[2] Equal0~13sexpbal lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.900 ns" { CLK {} CLK~out {} num1[2] {} Equal0~13sexpbal {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.200ns 3.800ns } { 0.000ns 2.400ns 2.400ns 4.000ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.400 ns" { START CS~18 lpm_counter:Address2_rtl_2|dffs[10]~807 lpm_counter:Address2_rtl_2|dffs[10]~812 lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.400 ns" { START {} START~out {} CS~18 {} lpm_counter:Address2_rtl_2|dffs[10]~807 {} lpm_counter:Address2_rtl_2|dffs[10]~812 {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.800ns 0.000ns 0.000ns } { 0.000ns 1.200ns 8.400ns 1.300ns 0.600ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "17.900 ns" { CLK num1[2] Equal0~13sexpbal lpm_counter:Address2_rtl_2|dffs[10] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "17.900 ns" { CLK {} CLK~out {} num1[2] {} Equal0~13sexpbal {} lpm_counter:Address2_rtl_2|dffs[10] {} } { 0.000ns 0.000ns 0.000ns 3.200ns 3.800ns } { 0.000ns 2.400ns 2.400ns 4.000ns 2.100ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK JV3 lpm_counter:NumVH_rtl_3\|dffs\[0\] 47.300 ns register " "Info: tco from clock \"CLK\" to destination pin \"JV3\" through register \"lpm_counter:NumVH_rtl_3\|dffs\[0\]\" is 47.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 25.200 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 25.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns CLK 1 CLK PIN_184 6 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_184; Fanout = 6; CLK Node = 'CLK'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 4.800 ns num1\[2\] 2 REG LC87 2 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 4.800 ns; Loc. = LC87; Fanout = 2; REG Node = 'num1\[2\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK num1[2] } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 12.000 ns Equal0~13sexpbal 3 COMB LC85 29 " "Info: 3: + IC(3.200 ns) + CELL(4.000 ns) = 12.000 ns; Loc. = LC85; Fanout = 29; COMB Node = 'Equal0~13sexpbal'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { num1[2] Equal0~13sexpbal } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(3.700 ns) 19.500 ns lpm_counter:NumRG_rtl_0\|dffs\[0\] 4 REG LC140 45 " "Info: 4: + IC(3.800 ns) + CELL(3.700 ns) = 19.500 ns; Loc. = LC140; Fanout = 45; REG Node = 'lpm_counter:NumRG_rtl_0\|dffs\[0\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { Equal0~13sexpbal lpm_counter:NumRG_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.100 ns) 25.200 ns lpm_counter:NumVH_rtl_3\|dffs\[0\] 5 REG LC255 49 " "Info: 5: + IC(3.600 ns) + CELL(2.100 ns) = 25.200 ns; Loc. = LC255; Fanout = 49; REG Node = 'lpm_counter:NumVH_rtl_3\|dffs\[0\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { lpm_counter:NumRG_rtl_0|dffs[0] lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.600 ns ( 57.94 % ) " "Info: Total cell delay = 14.600 ns ( 57.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.600 ns ( 42.06 % ) " "Info: Total interconnect delay = 10.600 ns ( 42.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "25.200 ns" { CLK num1[2] Equal0~13sexpbal lpm_counter:NumRG_rtl_0|dffs[0] lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "25.200 ns" { CLK {} CLK~out {} num1[2] {} Equal0~13sexpbal {} lpm_counter:NumRG_rtl_0|dffs[0] {} lpm_counter:NumVH_rtl_3|dffs[0] {} } { 0.000ns 0.000ns 0.000ns 3.200ns 3.800ns 3.600ns } { 0.000ns 2.400ns 2.400ns 4.000ns 3.700ns 2.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.500 ns + Longest register pin " "Info: + Longest register to pin delay is 20.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:NumVH_rtl_3\|dffs\[0\] 1 REG LC255 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC255; Fanout = 49; REG Node = 'lpm_counter:NumVH_rtl_3\|dffs\[0\]'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf" 283 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(3.700 ns) 7.700 ns Equal1~25sexp 2 COMB SEXP241 18 " "Info: 2: + IC(4.000 ns) + CELL(3.700 ns) = 7.700 ns; Loc. = SEXP241; Fanout = 18; COMB Node = 'Equal1~25sexp'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { lpm_counter:NumVH_rtl_3|dffs[0] Equal1~25sexp } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 11.700 ns V3~385 3 COMB LC244 3 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 11.700 ns; Loc. = LC244; Fanout = 3; COMB Node = 'V3~385'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Equal1~25sexp V3~385 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.200 ns) 18.900 ns V3~408 4 COMB LOOP LC246 3 " "Info: 4: + IC(0.000 ns) + CELL(7.200 ns) = 18.900 ns; Loc. = LC246; Fanout = 3; COMB LOOP Node = 'V3~408'" { { "Info" "ITDB_PART_OF_SCC" "V3~408 LC246 " "Info: Loc. = LC246; Node \"V3~408\"" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { V3~408 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { V3~408 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 20 -1 0 } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { V3~385 V3~408 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 20.500 ns JV3 5 PIN PIN_61 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 20.500 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'JV3'" {  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { V3~408 JV3 } "NODE_NAME" } } { "rs_ccd.vhd" "" { Text "D:/CCDVHDL/ICX408AL 75M/rs_ccd.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.500 ns ( 80.49 % ) " "Info: Total cell delay = 16.500 ns ( 80.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.51 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] Equal1~25sexp V3~385 V3~408 JV3 } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] {} Equal1~25sexp {} V3~385 {} V3~408 {} JV3 {} } { 0.000ns 4.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.700ns 4.000ns 7.200ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "25.200 ns" { CLK num1[2] Equal0~13sexpbal lpm_counter:NumRG_rtl_0|dffs[0] lpm_counter:NumVH_rtl_3|dffs[0] } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "25.200 ns" { CLK {} CLK~out {} num1[2] {} Equal0~13sexpbal {} lpm_counter:NumRG_rtl_0|dffs[0] {} lpm_counter:NumVH_rtl_3|dffs[0] {} } { 0.000ns 0.000ns 0.000ns 3.200ns 3.800ns 3.600ns } { 0.000ns 2.400ns 2.400ns 4.000ns 3.700ns 2.100ns } "" } } { "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] Equal1~25sexp V3~385 V3~408 JV3 } "NODE_NAME" } } { "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "20.500 ns" { lpm_counter:NumVH_rtl_3|dffs[0] {} Equal1~25sexp {} V3~385 {} V3~408 {} JV3 {} } { 0.000ns 4.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.700ns 4.000ns 7.200ns 1.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s!