rs_ccd.vhd.bak

基于CPLD的CCD驱动程序源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rs_ccd is
  port(
       CLK,START,ACLK,SUBTIME: in std_logic;
       RG,H1,H2,JV1,JV2,JV3,JV4,JXSG1,JXSG2,JSUB,INT0: out std_logic;
       SHP,SHD,CLKADC,CLOPB,CLPADC,WE,SUBINT1: out std_logic;  
       Address : out std_logic_vector(17 downto 0)   
       );
end rs_ccd;
architecture rs_out of rs_ccd is
signal num0: integer range 0 to 1:=0;
signal num1,num2: integer range 0 to 7:=0;
signal NumRG: integer range 0 to 923:=0;
signal NumVH: integer range 0 to 260:=0;
signal Address2,Address3: std_logic_vector(17 downto 0):="000000000000000000";
signal RGCLK,RGCLKA,VCLK,HD2,WE2,CS: std_logic;
signal V1,V2,V3,V4,XSG1,XSG2,SUB: std_logic;
begin


a2:process(CLK)                       --8分频电路
begin
if CLK'event and CLK='1' then
if num1<7 then                  
num1<=num1+1;
else
num1<=0;
end if;
end if;
end process a2;

a3: process(num1)
begin
if num1=0 then              -- 计数脉冲RGCLK
RGCLK<='0';
else
RGCLK<='1';
end if;
end process a3;

a4:process(VCLK)         --一帧基场信号，垂直移位V的计数值
begin
if VCLK'event and VCLK='1' then
if NumVH<260 then
 NumVH<=NumVH+1;
else
NumVH<=0;
end if;
end if;
end process a4;

a5:process(NumVH,RGCLK)        --如果垂直移位计数值NumVH=256，则SUBINT1向单片机发出中断1信号。
begin

if START='1' then
if NumVH=258 then        --单片机接收到中断1信号，则将SUBTIME信号置为低电平后，开始进行CCD曝光延时控制。
SUBINT1<='0';
else
SUBINT1<='1';
end if;
end if;

if RGCLK'event and RGCLK='1' then  --如果SUBTIME信号为高电平，则表示NumRG在计数，此时单片机没有发出曝光控制信号；
if SUBTIME='1' then  
if NumRG<923 then                   --此时单片机发出曝光控制信号，控制CCD曝光时间。
 NumRG<=NumRG+1;
else        
NumRG<=0;
end if;
end if;
end if;
end process a5;


a6:process(START,NumVH) 
begin
if START='1' then       --如果START为高电平信号，且NumVH=252时，CS信号高电平，
if NumVH=4 then       --如果START为低电平信号，CS信号为低电平，
CS<='1';                --这样从单片机转向CPLD计数地址的时候，可以保证CPLD必须在
end if;                 --NumVH=7时,开始使用CPLD计数，保证地址计数准确。
else
CS<='0';
end if;
end process a6;

a7:process(NumRG,CLK) 
begin
if NumRG<834 then
if CLK'event and CLK='1' then  --8分频电路
if num2<7 then                  
num2<=num2+1;
else
num2<=0;
end if;
end if;
else
num2<=0;
end if;
end process a7;

a8:process(num2)
begin
if num2>=0 and num2<=3 then
HD2<='0';
else
HD2<='1';
end if;

if num2=0 then                --复位脉冲RG
RG<='0';
else
RG<='1';
end if;

if num2=2 then               --双采样脉冲SHP         
SHP<='1';
else
SHP<='0';
end if;

if num2=5 then              --双采样脉冲SHD 
SHD<='1';
else
SHD<='0';
end if;

if num2=7 then             --ADC转换采样脉冲CLKADC 
CLKADC<='1';
else
CLKADC<='0';
end if;

if num2=4 then              
WE2<='0';
else
WE2<='1';
end if;

if START='1' then   --如果START信号为高电平，则由CPLD内的时钟信号对地址计数；
if CS='1' then      --且必须由单片机时钟转向CPLD时钟对地址计数的下一个周期CPLD才能计数。
if NumVH>=7 and NumVH<254 then
if NumRG>=27 and NumRG<=794 then 
WE<=WE2;
if RGCLK'event and RGCLK='1' then
if Address2<"101110010011111111" then
Address2<=Address2+1;
INT0<='1';
else
INT0<='0';
Address2<="000000000000000000";
end if;
end if;
else
WE<='1';
end if;
end if;
end if;
Address<=Address2;
Address3<="000000000000000000";

elsif START='0' then               --如果START信号为低电平，则由单片机产生的时钟信号对地址计数；
if ACLK'event and ACLK='1' then
if Address3<"101110010011111111" then
Address3<=Address3+1;
else
Address3<="000000000000000000";
end if;
end if;
Address<=Address3;
Address2<="000000000000000000";
end if;

end process a8;

a9:process(NumRG)      --进行黑电平钳位信号
begin
if NumRG>=795 and NumRG<830 then
CLOPB<='1';
CLPADC<='1';
else
CLOPB<='0';
CLPADC<='0';
end if;
end process a9;

a10:process(NumRG)
begin
if NumRG=923 then
VCLK<='1';
else
VCLK<='0';
end if;
end process a10;

a11: process(NumVH,NumRG)     
begin
if NumVH=0 then                    --1帧信号，垂直移位脉冲相位关系
if NumRG>=0 and NumRG<238 then     -- 移动一行，垂直移位脉冲相位关系
V1<='1';V2<='1';V3<='0';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=238 and NumRG<240 then
V1<='1';V2<='0';V3<='0';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=240 and NumRG<252 then
V1<='1';V2<='0';V3<='1';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=252 and NumRG<272 then
V1<='1';V2<='0';V3<='1';V4<='0';SUB<='0';XSG1<='1';XSG2<='0';
elsif NumRG>=272 and NumRG<292 then
V1<='1';V2<='0';V3<='1';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=292 and NumRG<312 then
V1<='1';V2<='0';V3<='1';V4<='0';SUB<='0';XSG1<='0';XSG2<='1';
elsif NumRG>=312 and NumRG<330 then
V1<='1';V2<='0';V3<='1';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=330 and NumRG<364 then
V1<='1';V2<='1';V3<='1';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=364 and NumRG<374 then
V1<='0';V2<='1';V3<='1';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=374 and NumRG<384 then
V1<='0';V2<='1';V3<='1';V4<='1';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=384 and NumRG<394 then
V1<='0';V2<='0';V3<='1';V4<='1';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=394 and NumRG<404 then
V1<='1';V2<='0';V3<='1';V4<='1';SUB<='0';XSG1<='0';XSG2<='0';
elsif NumRG>=404 and NumRG<414 then
V1<='1';V2<='0';V3<='0';V4<='1';SUB<='1';XSG1<='0';XSG2<='0';
elsif NumRG>=414 and NumRG<424 then
V1<='1';V2<='1';V3<='0';V4<='1';SUB<='1';XSG1<='0';XSG2<='0';
elsif NumRG>=424 and NumRG<434 then
V1<='1';V2<='1';V3<='0';V4<='0';SUB<='1';XSG1<='0';XSG2<='0';
elsif NumRG>=434 then
V1<='1';V2<='1';V3<='0';V4<='0';SUB<='0';XSG1<='0';XSG2<='0';
end if;

else                      --1帧信号中，奇场信号XSG1,XSG2与V1,V2,V3,V4的相位关系
if NumRG<834 then     
V1<='1';V2<='1';V3<='0';V4<='0';SUB<='0';
elsif NumRG>=834 and NumRG<844 then     
V1<='1';V2<='1';V3<='1';V4<='0';SUB<='0';
elsif NumRG>=844 and NumRG<854 then
V1<='0';V2<='1';V3<='1';V4<='0';SUB<='0';
elsif NumRG>=854 and NumRG<864 then
V1<='0';V2<='1';V3<='1';V4<='1';SUB<='0';
elsif NumRG>=864 and NumRG<874 then
V1<='0';V2<='0';V3<='1';V4<='1';SUB<='0';
elsif NumRG>=874 and NumRG<884 then
V1<='1';V2<='0';V3<='1';V4<='1';SUB<='0';
elsif NumRG>=884 and NumRG<894 then
V1<='1';V2<='0';V3<='0';V4<='1';SUB<='1';
elsif NumRG>=894 and NumRG<904 then
V1<='1';V2<='1';V4<='1';SUB<='1';
elsif NumRG>=904 and NumRG<914 then
V1<='1';V2<='1';V4<='0';SUB<='1';
elsif NumRG>=914 then
V1<='1';V2<='1';V3<='0';V4<='0';SUB<='0';
end if;
end if;
end process a11;

H2<=not HD2;

JV1<=not V1;
JV2<=not V2;
JV3<=not V3;
JV4<=not V4;
JSUB<=not SUB;
JXSG1<=not XSG1;
JXSG2<=not XSG2;



end rs_out;