📄 rs_ccd.map.rpt
字号:
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:Address2_rtl_2 ;
+------------------------+-------------------+--------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+--------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 18 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:NumVH_rtl_3 ;
+------------------------+-------------------+-----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-----------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 9 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; MAX3000A ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue Feb 10 11:32:45 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rs_ccd -c rs_ccd
Info: Found 2 design units, including 1 entities, in source file rs_ccd.vhd
Info: Found design unit 1: rs_ccd-rs_out
Info: Found entity 1: rs_ccd
Info: Elaborating entity "rs_ccd" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(58): signal "START" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(55): inferring latch(es) for signal or variable "SUBINT1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(78): inferring latch(es) for signal or variable "CS", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(142): signal "START" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(143): signal "CS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(144): signal "NumVH" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(145): signal "NumRG" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(146): signal "WE2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(147): signal "RGCLK" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(161): signal "Address2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(164): signal "START" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(165): signal "ACLK" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at rs_ccd.vhd(172): signal "Address3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(104): inferring latch(es) for signal or variable "WE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(104): inferring latch(es) for signal or variable "Address", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "V1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "V2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "V3", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "V4", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "SUB", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "XSG1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at rs_ccd.vhd(198): inferring latch(es) for signal or variable "XSG2", which holds its previous value in one or more paths through the process
Warning (10034): Output port "H1" at rs_ccd.vhd(8) has no driver
Info (10041): Inferred latch for "XSG2" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "XSG1" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "SUB" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "V4" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "V3" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "V2" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "V1" at rs_ccd.vhd(198)
Info (10041): Inferred latch for "WE" at rs_ccd.vhd(104)
Info (10041): Inferred latch for "CS" at rs_ccd.vhd(78)
Info (10041): Inferred latch for "SUBINT1" at rs_ccd.vhd(55)
Info: Inferred 4 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: "NumRG[0]~308"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=18) from the following logic: "Address3[0]~18"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=18) from the following logic: "Address2[0]~621"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "NumVH[0]~9"
Info: Found 1 design units, including 1 entities, in source file e:/program files/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:NumRG_rtl_0"
Info: Elaborated megafunction instantiation "lpm_counter:Address3_rtl_1"
Info: Elaborated megafunction instantiation "lpm_counter:Address2_rtl_2"
Info: Elaborated megafunction instantiation "lpm_counter:NumVH_rtl_3"
Warning: LATCH primitive "V1" is permanently enabled
Warning: LATCH primitive "V2" is permanently enabled
Warning: LATCH primitive "V4" is permanently enabled
Warning: LATCH primitive "SUB" is permanently enabled
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "H1" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "CLK" to global clock signal
Info: Implemented 242 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 36 output pins
Info: Implemented 181 macrocells
Info: Implemented 21 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings
Info: Allocated 159 megabytes of memory during processing
Info: Processing ended: Tue Feb 10 11:32:55 2009
Info: Elapsed time: 00:00:10
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -