in8031.map.qmsg

8031仿真程序 用VHDL硬件描述语言写的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 05 10:05:19 2008 " "Info: Processing started: Wed Nov 05 10:05:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off in8031 -c in8031 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off in8031 -c in8031" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "in8031.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file in8031.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 in8031-in8031 " "Info: Found design unit 1: in8031-in8031" {  } { { "in8031.vhd" "" { Text "E:/wgh/quartus程序/8031仿真/in8031.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 in8031 " "Info: Found entity 1: in8031" {  } { { "in8031.vhd" "" { Text "E:/wgh/quartus程序/8031仿真/in8031.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "in8031 " "Info: Elaborating entity \"in8031\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "clk in8031.vhd(11) " "Warning (10036): Verilog HDL or VHDL warning at in8031.vhd(11): object \"clk\" assigned a value but never read" {  } { { "in8031.vhd" "" { Text "E:/wgh/quartus程序/8031仿真/in8031.vhd" 11 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "rst in8031.vhd(11) " "Warning (10036): Verilog HDL or VHDL warning at in8031.vhd(11): object \"rst\" assigned a value but never read" {  } { { "in8031.vhd" "" { Text "E:/wgh/quartus程序/8031仿真/in8031.vhd" 11 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Error" "EVRFX_VHDL_WAIT_W_O_UNTIL" "in8031.vhd(15) " "Error (10533): VHDL Wait Statement error at in8031.vhd(15): Wait Statement must contain condition clause with UNTIL keyword" {  } { { "in8031.vhd" "" { Text "E:/wgh/quartus程序/8031仿真/in8031.vhd" 15 0 0 } }  } 0 10533 "VHDL Wait Statement error at %1!s!: Wait Statement must contain condition clause with UNTIL keyword" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 2 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Nov 05 10:05:19 2008 " "Error: Processing ended: Wed Nov 05 10:05:19 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}