my_component.vhd

How to infer a finite state machine for fpga altera xilinx

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity my_component is  
generic ( array_size: positive :=2);
port(   clk:   in std_logic;
        rst:   in std_logic;
        in_A :  in signed  (array_size-1 downto 0);
        out_A:  out signed (array_size-1 downto 0));
end my_component;

architecture my_architecture of my_component is

begin

process(clk,rst)
begin

      if (rst = '1') then
      out_A <= (others => '0');
      elsif rising_edge (clk) then
      out_A <= in_A;
      end if;
      
end process;

end my_architecture;