📄 c_a.tan.rpt
字号:
; N/A ; None ; 1.793 ns ; clr ; Q2[10]~reg0 ; clk ;
; N/A ; None ; 1.792 ns ; clr ; Q2[5]~reg0 ; clk ;
; N/A ; None ; 1.792 ns ; clr ; Q2[6]~reg0 ; clk ;
; N/A ; None ; 1.791 ns ; clr ; Q2[2]~reg0 ; clk ;
; N/A ; None ; 1.787 ns ; clr ; Q2[3]~reg0 ; clk ;
; N/A ; None ; 1.786 ns ; clr ; Q2[9]~reg0 ; clk ;
; N/A ; None ; 1.784 ns ; clr ; Q2[8]~reg0 ; clk ;
; N/A ; None ; 1.784 ns ; clr ; Q2[7]~reg0 ; clk ;
+-------+--------------+------------+------+-------------+----------+
+-----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A ; None ; 7.703 ns ; Q1[1]~reg0 ; Q1[0] ; clk ;
; N/A ; None ; 7.698 ns ; Q1[1]~reg0 ; Q1[1] ; clk ;
; N/A ; None ; 7.635 ns ; Q2[10]~reg0 ; Q2[10] ; clk ;
; N/A ; None ; 7.205 ns ; Q2[8]~reg0 ; Q2[8] ; clk ;
; N/A ; None ; 6.940 ns ; Q2[1]~reg0 ; Q2[1] ; clk ;
; N/A ; None ; 6.940 ns ; Q2[1]~reg0 ; Q2[0] ; clk ;
; N/A ; None ; 6.899 ns ; G2~reg0 ; G2 ; clk ;
; N/A ; None ; 6.886 ns ; c_a~reg0 ; c_a ; clk ;
; N/A ; None ; 6.881 ns ; G1~reg0 ; G1 ; clk ;
; N/A ; None ; 6.879 ns ; Q1[5]~reg0 ; Q1[5] ; clk ;
; N/A ; None ; 6.878 ns ; Q1[8]~reg0 ; Q1[8] ; clk ;
; N/A ; None ; 6.875 ns ; Q2[7]~reg0 ; Q2[7] ; clk ;
; N/A ; None ; 6.869 ns ; Q1[7]~reg0 ; Q1[7] ; clk ;
; N/A ; None ; 6.844 ns ; Q1[4]~reg0 ; Q1[4] ; clk ;
; N/A ; None ; 6.841 ns ; Q1[3]~reg0 ; Q1[3] ; clk ;
; N/A ; None ; 6.714 ns ; Q2[5]~reg0 ; Q2[5] ; clk ;
; N/A ; None ; 6.709 ns ; Q2[6]~reg0 ; Q2[6] ; clk ;
; N/A ; None ; 6.674 ns ; Q1[10]~reg0 ; Q1[10] ; clk ;
; N/A ; None ; 6.662 ns ; Q1[6]~reg0 ; Q1[6] ; clk ;
; N/A ; None ; 6.495 ns ; Q2[4]~reg0 ; Q2[4] ; clk ;
; N/A ; None ; 6.490 ns ; Q2[3]~reg0 ; Q2[3] ; clk ;
; N/A ; None ; 6.485 ns ; Q2[2]~reg0 ; Q2[2] ; clk ;
; N/A ; None ; 6.455 ns ; Q1[2]~reg0 ; Q1[2] ; clk ;
; N/A ; None ; 6.322 ns ; Q2[9]~reg0 ; Q2[9] ; clk ;
; N/A ; None ; 6.295 ns ; Q1[9]~reg0 ; Q1[9] ; clk ;
+-------+--------------+------------+-------------+--------+------------+
+-------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A ; None ; -1.674 ns ; clr ; Q2[8]~reg0 ; clk ;
; N/A ; None ; -1.674 ns ; clr ; Q2[7]~reg0 ; clk ;
; N/A ; None ; -1.676 ns ; clr ; Q2[9]~reg0 ; clk ;
; N/A ; None ; -1.677 ns ; clr ; Q2[3]~reg0 ; clk ;
; N/A ; None ; -1.681 ns ; clr ; Q2[2]~reg0 ; clk ;
; N/A ; None ; -1.682 ns ; clr ; Q2[5]~reg0 ; clk ;
; N/A ; None ; -1.682 ns ; clr ; Q2[6]~reg0 ; clk ;
; N/A ; None ; -1.683 ns ; clr ; Q2[10]~reg0 ; clk ;
; N/A ; None ; -1.767 ns ; clr ; Q2[4]~reg0 ; clk ;
; N/A ; None ; -1.771 ns ; clr ; Q1[9]~reg0 ; clk ;
; N/A ; None ; -1.772 ns ; clr ; Q1[4]~reg0 ; clk ;
; N/A ; None ; -1.773 ns ; clr ; Q1[7]~reg0 ; clk ;
; N/A ; None ; -1.774 ns ; clr ; Q1[2]~reg0 ; clk ;
; N/A ; None ; -1.778 ns ; clr ; Q1[3]~reg0 ; clk ;
; N/A ; None ; -1.780 ns ; clr ; Q1[6]~reg0 ; clk ;
; N/A ; None ; -1.780 ns ; clr ; Q1[10]~reg0 ; clk ;
; N/A ; None ; -1.781 ns ; clr ; Q1[5]~reg0 ; clk ;
; N/A ; None ; -1.782 ns ; clr ; Q1[8]~reg0 ; clk ;
; N/A ; None ; -1.896 ns ; clr ; Q2[1]~reg0 ; clk ;
; N/A ; None ; -2.254 ns ; clr ; G1~reg0 ; clk ;
; N/A ; None ; -2.254 ns ; clr ; G2~reg0 ; clk ;
; N/A ; None ; -2.254 ns ; clr ; c_a~reg0 ; clk ;
; N/A ; None ; -2.415 ns ; clr ; Q1[1]~reg0 ; clk ;
+---------------+-------------+-----------+------+-------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Feb 27 15:44:31 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off c_a -c c_a --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "Q1[9]~reg0" and destination register "c_a~reg0"
Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.261 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y7_N7; Fanout = 4; REG Node = 'Q1[9]~reg0'
Info: 2: + IC(1.038 ns) + CELL(0.223 ns) = 1.261 ns; Loc. = LC_X51_Y10_N4; Fanout = 1; REG Node = 'c_a~reg0'
Info: Total cell delay = 0.223 ns ( 17.68 % )
Info: Total interconnect delay = 1.038 ns ( 82.32 % )
Info: - Smallest clock skew is 0.034 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.986 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'
Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X51_Y10_N4; Fanout = 1; REG Node = 'c_a~reg0'
Info: Total cell delay = 1.370 ns ( 45.88 % )
Info: Total interconnect delay = 1.616 ns ( 54.12 % )
Info: - Longest clock path from clock "clk" to source register is 2.952 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'
Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X52_Y7_N7; Fanout = 4; REG Node = 'Q1[9]~reg0'
Info: Total cell delay = 1.370 ns ( 46.41 % )
Info: Total interconnect delay = 1.582 ns ( 53.59 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "Q1[1]~reg0" (data pin = "clr", clock pin = "clk") is 2.525 ns
Info: + Longest pin to register delay is 5.467 ns
Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 23; PIN Node = 'clr'
Info: 2: + IC(3.872 ns) + CELL(0.870 ns) = 5.467 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1[1]~reg0'
Info: Total cell delay = 1.595 ns ( 29.18 % )
Info: Total interconnect delay = 3.872 ns ( 70.82 % )
Info: + Micro setup delay of destination is 0.010 ns
Info: - Shortest clock path from clock "clk" to destination register is 2.952 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'
Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1[1]~reg0'
Info: Total cell delay = 1.370 ns ( 46.41 % )
Info: Total interconnect delay = 1.582 ns ( 53.59 % )
Info: tco from clock "clk" to destination pin "Q1[0]" through register "Q1[1]~reg0" is 7.703 ns
Info: + Longest clock path from clock "clk" to source register is 2.952 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'
Info: 2: + IC(1.582 ns) + CELL(0.542 ns) = 2.952 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1[1]~reg0'
Info: Total cell delay = 1.370 ns ( 46.41 % )
Info: Total interconnect delay = 1.582 ns ( 53.59 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 4.595 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y7_N1; Fanout = 4; REG Node = 'Q1[1]~reg0'
Info: 2: + IC(2.219 ns) + CELL(2.376 ns) = 4.595 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'Q1[0]'
Info: Total cell delay = 2.376 ns ( 51.71 % )
Info: Total interconnect delay = 2.219 ns ( 48.29 % )
Info: th for register "Q2[8]~reg0" (data pin = "clr", clock pin = "clk") is -1.674 ns
Info: + Longest clock path from clock "clk" to destination register is 2.986 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 23; CLK Node = 'clk'
Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 3; REG Node = 'Q2[8]~reg0'
Info: Total cell delay = 1.370 ns ( 45.88 % )
Info: Total interconnect delay = 1.616 ns ( 54.12 % )
Info: + Micro hold delay of destination is 0.100 ns
Info: - Shortest pin to register delay is 4.760 ns
Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 23; PIN Node = 'clr'
Info: 2: + IC(3.812 ns) + CELL(0.223 ns) = 4.760 ns; Loc. = LC_X52_Y10_N7; Fanout = 3; REG Node = 'Q2[8]~reg0'
Info: Total cell delay = 0.948 ns ( 19.92 % )
Info: Total interconnect delay = 3.812 ns ( 80.08 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Feb 27 15:44:33 2009
Info: Elapsed time: 00:00:03
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -