c_a.map.qmsg

GPS中C/A码产生简单的Verilog逻辑产生

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 27 15:43:43 2009 " "Info: Processing started: Fri Feb 27 15:43:43 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off c_a -c c_a " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off c_a -c c_a" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "c_a c_a.v(1) " "Warning (10238): Verilog Module Declaration warning at c_a.v(1): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"c_a\"" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 1 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c_a.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file c_a.v" { { "Info" "ISGN_ENTITY_NAME" "1 c_a " "Info: Found entity 1: c_a" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "c_a " "Info: Elaborating entity \"c_a\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Q1\[0\]~reg0 Q1\[1\]~reg0 " "Info: Duplicate register \"Q1\[0\]~reg0\" merged to single register \"Q1\[1\]~reg0\"" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Q2\[0\]~reg0 Q2\[1\]~reg0 " "Info: Duplicate register \"Q2\[0\]~reg0\" merged to single register \"Q2\[1\]~reg0\"" {  } { { "c_a.v" "" { Text "D:/alter/quartusII/newprojec/c_a/c_a.v" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "52 " "Info: Implemented 52 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "25 " "Info: Implemented 25 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 27 15:43:46 2009 " "Info: Processing ended: Fri Feb 27 15:43:46 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}