c_a.map.summary

GPS中C/A码产生简单的Verilog逻辑产生

Analysis & Synthesis Status : Successful - Fri Feb 27 15:43:46 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : c_a
Top-level Entity Name : c_a
Family : Stratix
Total logic elements : 25
Total pins : 27
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0