c_a.vo

GPS中C/A码产生简单的Verilog逻辑产生

// synopsys translate_on

// atom is at PIN_P6
stratix_io \Q2[1]~I (
	.datain(\Q2[1]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[1]~I .ddio_mode = "none";
defparam \Q2[1]~I .input_async_reset = "none";
defparam \Q2[1]~I .input_power_up = "low";
defparam \Q2[1]~I .input_register_mode = "none";
defparam \Q2[1]~I .input_sync_reset = "none";
defparam \Q2[1]~I .oe_async_reset = "none";
defparam \Q2[1]~I .oe_power_up = "low";
defparam \Q2[1]~I .oe_register_mode = "none";
defparam \Q2[1]~I .oe_sync_reset = "none";
defparam \Q2[1]~I .operation_mode = "output";
defparam \Q2[1]~I .output_async_reset = "none";
defparam \Q2[1]~I .output_power_up = "low";
defparam \Q2[1]~I .output_register_mode = "none";
defparam \Q2[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_R2
stratix_io \Q2[2]~I (
	.datain(\Q2[2]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[2]~I .ddio_mode = "none";
defparam \Q2[2]~I .input_async_reset = "none";
defparam \Q2[2]~I .input_power_up = "low";
defparam \Q2[2]~I .input_register_mode = "none";
defparam \Q2[2]~I .input_sync_reset = "none";
defparam \Q2[2]~I .oe_async_reset = "none";
defparam \Q2[2]~I .oe_power_up = "low";
defparam \Q2[2]~I .oe_register_mode = "none";
defparam \Q2[2]~I .oe_sync_reset = "none";
defparam \Q2[2]~I .operation_mode = "output";
defparam \Q2[2]~I .output_async_reset = "none";
defparam \Q2[2]~I .output_power_up = "low";
defparam \Q2[2]~I .output_register_mode = "none";
defparam \Q2[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_P2
stratix_io \Q2[3]~I (
	.datain(\Q2[3]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[3]~I .ddio_mode = "none";
defparam \Q2[3]~I .input_async_reset = "none";
defparam \Q2[3]~I .input_power_up = "low";
defparam \Q2[3]~I .input_register_mode = "none";
defparam \Q2[3]~I .input_sync_reset = "none";
defparam \Q2[3]~I .oe_async_reset = "none";
defparam \Q2[3]~I .oe_power_up = "low";
defparam \Q2[3]~I .oe_register_mode = "none";
defparam \Q2[3]~I .oe_sync_reset = "none";
defparam \Q2[3]~I .operation_mode = "output";
defparam \Q2[3]~I .output_async_reset = "none";
defparam \Q2[3]~I .output_power_up = "low";
defparam \Q2[3]~I .output_register_mode = "none";
defparam \Q2[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_P3
stratix_io \Q2[4]~I (
	.datain(\Q2[4]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[4]~I .ddio_mode = "none";
defparam \Q2[4]~I .input_async_reset = "none";
defparam \Q2[4]~I .input_power_up = "low";
defparam \Q2[4]~I .input_register_mode = "none";
defparam \Q2[4]~I .input_sync_reset = "none";
defparam \Q2[4]~I .oe_async_reset = "none";
defparam \Q2[4]~I .oe_power_up = "low";
defparam \Q2[4]~I .oe_register_mode = "none";
defparam \Q2[4]~I .oe_sync_reset = "none";
defparam \Q2[4]~I .operation_mode = "output";
defparam \Q2[4]~I .output_async_reset = "none";
defparam \Q2[4]~I .output_power_up = "low";
defparam \Q2[4]~I .output_register_mode = "none";
defparam \Q2[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_N2
stratix_io \Q2[5]~I (
	.datain(\Q2[5]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[5]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[5]~I .ddio_mode = "none";
defparam \Q2[5]~I .input_async_reset = "none";
defparam \Q2[5]~I .input_power_up = "low";
defparam \Q2[5]~I .input_register_mode = "none";
defparam \Q2[5]~I .input_sync_reset = "none";
defparam \Q2[5]~I .oe_async_reset = "none";
defparam \Q2[5]~I .oe_power_up = "low";
defparam \Q2[5]~I .oe_register_mode = "none";
defparam \Q2[5]~I .oe_sync_reset = "none";
defparam \Q2[5]~I .operation_mode = "output";
defparam \Q2[5]~I .output_async_reset = "none";
defparam \Q2[5]~I .output_power_up = "low";
defparam \Q2[5]~I .output_register_mode = "none";
defparam \Q2[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_T1
stratix_io \Q2[6]~I (
	.datain(\Q2[6]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[6]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[6]~I .ddio_mode = "none";
defparam \Q2[6]~I .input_async_reset = "none";
defparam \Q2[6]~I .input_power_up = "low";
defparam \Q2[6]~I .input_register_mode = "none";
defparam \Q2[6]~I .input_sync_reset = "none";
defparam \Q2[6]~I .oe_async_reset = "none";
defparam \Q2[6]~I .oe_power_up = "low";
defparam \Q2[6]~I .oe_register_mode = "none";
defparam \Q2[6]~I .oe_sync_reset = "none";
defparam \Q2[6]~I .operation_mode = "output";
defparam \Q2[6]~I .output_async_reset = "none";
defparam \Q2[6]~I .output_power_up = "low";
defparam \Q2[6]~I .output_register_mode = "none";
defparam \Q2[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_M6
stratix_io \Q2[7]~I (
	.datain(\Q2[7]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[7]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[7]~I .ddio_mode = "none";
defparam \Q2[7]~I .input_async_reset = "none";
defparam \Q2[7]~I .input_power_up = "low";
defparam \Q2[7]~I .input_register_mode = "none";
defparam \Q2[7]~I .input_sync_reset = "none";
defparam \Q2[7]~I .oe_async_reset = "none";
defparam \Q2[7]~I .oe_power_up = "low";
defparam \Q2[7]~I .oe_register_mode = "none";
defparam \Q2[7]~I .oe_sync_reset = "none";
defparam \Q2[7]~I .operation_mode = "output";
defparam \Q2[7]~I .output_async_reset = "none";
defparam \Q2[7]~I .output_power_up = "low";
defparam \Q2[7]~I .output_register_mode = "none";
defparam \Q2[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K2
stratix_io \Q2[8]~I (
	.datain(\Q2[8]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[8]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[8]~I .ddio_mode = "none";
defparam \Q2[8]~I .input_async_reset = "none";
defparam \Q2[8]~I .input_power_up = "low";
defparam \Q2[8]~I .input_register_mode = "none";
defparam \Q2[8]~I .input_sync_reset = "none";
defparam \Q2[8]~I .oe_async_reset = "none";
defparam \Q2[8]~I .oe_power_up = "low";
defparam \Q2[8]~I .oe_register_mode = "none";
defparam \Q2[8]~I .oe_sync_reset = "none";
defparam \Q2[8]~I .operation_mode = "output";
defparam \Q2[8]~I .output_async_reset = "none";
defparam \Q2[8]~I .output_power_up = "low";
defparam \Q2[8]~I .output_register_mode = "none";
defparam \Q2[8]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_R1
stratix_io \Q2[9]~I (
	.datain(\Q2[9]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[9]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[9]~I .ddio_mode = "none";
defparam \Q2[9]~I .input_async_reset = "none";
defparam \Q2[9]~I .input_power_up = "low";
defparam \Q2[9]~I .input_register_mode = "none";
defparam \Q2[9]~I .input_sync_reset = "none";
defparam \Q2[9]~I .oe_async_reset = "none";
defparam \Q2[9]~I .oe_power_up = "low";
defparam \Q2[9]~I .oe_register_mode = "none";
defparam \Q2[9]~I .oe_sync_reset = "none";
defparam \Q2[9]~I .operation_mode = "output";
defparam \Q2[9]~I .output_async_reset = "none";
defparam \Q2[9]~I .output_power_up = "low";
defparam \Q2[9]~I .output_register_mode = "none";
defparam \Q2[9]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J2
stratix_io \Q2[10]~I (
	.datain(\Q2[10]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[10]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[10]~I .ddio_mode = "none";
defparam \Q2[10]~I .input_async_reset = "none";
defparam \Q2[10]~I .input_power_up = "low";
defparam \Q2[10]~I .input_register_mode = "none";
defparam \Q2[10]~I .input_sync_reset = "none";
defparam \Q2[10]~I .oe_async_reset = "none";
defparam \Q2[10]~I .oe_power_up = "low";
defparam \Q2[10]~I .oe_register_mode = "none";
defparam \Q2[10]~I .oe_sync_reset = "none";
defparam \Q2[10]~I .operation_mode = "output";
defparam \Q2[10]~I .output_async_reset = "none";
defparam \Q2[10]~I .output_power_up = "low";
defparam \Q2[10]~I .output_register_mode = "none";
defparam \Q2[10]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_T2
stratix_io \G1~I (
	.datain(\G1~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(G1),
	.dqsundelayedout());
// synopsys translate_off
defparam \G1~I .ddio_mode = "none";
defparam \G1~I .input_async_reset = "none";
defparam \G1~I .input_power_up = "low";
defparam \G1~I .input_register_mode = "none";
defparam \G1~I .input_sync_reset = "none";
defparam \G1~I .oe_async_reset = "none";
defparam \G1~I .oe_power_up = "low";
defparam \G1~I .oe_register_mode = "none";
defparam \G1~I .oe_sync_reset = "none";
defparam \G1~I .operation_mode = "output";
defparam \G1~I .output_async_reset = "none";
defparam \G1~I .output_power_up = "low";
defparam \G1~I .output_register_mode = "none";
defparam \G1~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_U2
stratix_io \G2~I (
	.datain(\G2~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(G2),
	.dqsundelayedout());
// synopsys translate_off
defparam \G2~I .ddio_mode = "none";
defparam \G2~I .input_async_reset = "none";
defparam \G2~I .input_power_up = "low";
defparam \G2~I .input_register_mode = "none";
defparam \G2~I .input_sync_reset = "none";
defparam \G2~I .oe_async_reset = "none";
defparam \G2~I .oe_power_up = "low";
defparam \G2~I .oe_register_mode = "none";
defparam \G2~I .oe_sync_reset = "none";
defparam \G2~I .operation_mode = "output";
defparam \G2~I .output_async_reset = "none";
defparam \G2~I .output_power_up = "low";
defparam \G2~I .output_register_mode = "none";
defparam \G2~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_N3
stratix_io \c_a~I (
	.datain(\c_a~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(c_a),
	.dqsundelayedout());
// synopsys translate_off
defparam \c_a~I .ddio_mode = "none";
defparam \c_a~I .input_async_reset = "none";
defparam \c_a~I .input_power_up = "low";
defparam \c_a~I .input_register_mode = "none";
defparam \c_a~I .input_sync_reset = "none";
defparam \c_a~I .oe_async_reset = "none";
defparam \c_a~I .oe_power_up = "low";
defparam \c_a~I .oe_register_mode = "none";
defparam \c_a~I .oe_sync_reset = "none";
defparam \c_a~I .operation_mode = "output";
defparam \c_a~I .output_async_reset = "none";
defparam \c_a~I .output_power_up = "low";
defparam \c_a~I .output_register_mode = "none";
defparam \c_a~I .output_sync_reset = "none";
// synopsys translate_on

endmodule