c_a.vo

GPS中C/A码产生简单的Verilog逻辑产生

	.cout1());
// synopsys translate_off
defparam \G2~reg0_I .lut_mask = "0000";
defparam \G2~reg0_I .operation_mode = "normal";
defparam \G2~reg0_I .output_mode = "reg_only";
defparam \G2~reg0_I .register_cascade_mode = "off";
defparam \G2~reg0_I .sum_lutc_input = "datac";
defparam \G2~reg0_I .synch_mode = "on";
// synopsys translate_on

// atom is at LC_X51_Y10_N4
stratix_lcell \c_a~reg0_I (
// Equation(s):
// \c_a~reg0  = DFFEAS(\Q2[9]~reg0  $ \Q1[9]~reg0 , GLOBAL(\clk~combout ), VCC, , \clr~combout , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Q2[9]~reg0 ),
	.datad(\Q1[9]~reg0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\clr~combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\c_a~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \c_a~reg0_I .lut_mask = "0FF0";
defparam \c_a~reg0_I .operation_mode = "normal";
defparam \c_a~reg0_I .output_mode = "reg_only";
defparam \c_a~reg0_I .register_cascade_mode = "off";
defparam \c_a~reg0_I .sum_lutc_input = "datac";
defparam \c_a~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_H1
stratix_io \Q1[0]~I (
	.datain(\Q1[1]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[0]~I .ddio_mode = "none";
defparam \Q1[0]~I .input_async_reset = "none";
defparam \Q1[0]~I .input_power_up = "low";
defparam \Q1[0]~I .input_register_mode = "none";
defparam \Q1[0]~I .input_sync_reset = "none";
defparam \Q1[0]~I .oe_async_reset = "none";
defparam \Q1[0]~I .oe_power_up = "low";
defparam \Q1[0]~I .oe_register_mode = "none";
defparam \Q1[0]~I .oe_sync_reset = "none";
defparam \Q1[0]~I .operation_mode = "output";
defparam \Q1[0]~I .output_async_reset = "none";
defparam \Q1[0]~I .output_power_up = "low";
defparam \Q1[0]~I .output_register_mode = "none";
defparam \Q1[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_K3
stratix_io \Q1[1]~I (
	.datain(\Q1[1]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[1]~I .ddio_mode = "none";
defparam \Q1[1]~I .input_async_reset = "none";
defparam \Q1[1]~I .input_power_up = "low";
defparam \Q1[1]~I .input_register_mode = "none";
defparam \Q1[1]~I .input_sync_reset = "none";
defparam \Q1[1]~I .oe_async_reset = "none";
defparam \Q1[1]~I .oe_power_up = "low";
defparam \Q1[1]~I .oe_register_mode = "none";
defparam \Q1[1]~I .oe_sync_reset = "none";
defparam \Q1[1]~I .operation_mode = "output";
defparam \Q1[1]~I .output_async_reset = "none";
defparam \Q1[1]~I .output_power_up = "low";
defparam \Q1[1]~I .output_register_mode = "none";
defparam \Q1[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_R3
stratix_io \Q1[2]~I (
	.datain(\Q1[2]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[2]~I .ddio_mode = "none";
defparam \Q1[2]~I .input_async_reset = "none";
defparam \Q1[2]~I .input_power_up = "low";
defparam \Q1[2]~I .input_register_mode = "none";
defparam \Q1[2]~I .input_sync_reset = "none";
defparam \Q1[2]~I .oe_async_reset = "none";
defparam \Q1[2]~I .oe_power_up = "low";
defparam \Q1[2]~I .oe_register_mode = "none";
defparam \Q1[2]~I .oe_sync_reset = "none";
defparam \Q1[2]~I .operation_mode = "output";
defparam \Q1[2]~I .output_async_reset = "none";
defparam \Q1[2]~I .output_power_up = "low";
defparam \Q1[2]~I .output_register_mode = "none";
defparam \Q1[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_P4
stratix_io \Q1[3]~I (
	.datain(\Q1[3]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[3]~I .ddio_mode = "none";
defparam \Q1[3]~I .input_async_reset = "none";
defparam \Q1[3]~I .input_power_up = "low";
defparam \Q1[3]~I .input_register_mode = "none";
defparam \Q1[3]~I .input_sync_reset = "none";
defparam \Q1[3]~I .oe_async_reset = "none";
defparam \Q1[3]~I .oe_power_up = "low";
defparam \Q1[3]~I .oe_register_mode = "none";
defparam \Q1[3]~I .oe_sync_reset = "none";
defparam \Q1[3]~I .operation_mode = "output";
defparam \Q1[3]~I .output_async_reset = "none";
defparam \Q1[3]~I .output_power_up = "low";
defparam \Q1[3]~I .output_register_mode = "none";
defparam \Q1[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_N6
stratix_io \Q1[4]~I (
	.datain(\Q1[4]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[4]~I .ddio_mode = "none";
defparam \Q1[4]~I .input_async_reset = "none";
defparam \Q1[4]~I .input_power_up = "low";
defparam \Q1[4]~I .input_register_mode = "none";
defparam \Q1[4]~I .input_sync_reset = "none";
defparam \Q1[4]~I .oe_async_reset = "none";
defparam \Q1[4]~I .oe_power_up = "low";
defparam \Q1[4]~I .oe_register_mode = "none";
defparam \Q1[4]~I .oe_sync_reset = "none";
defparam \Q1[4]~I .operation_mode = "output";
defparam \Q1[4]~I .output_async_reset = "none";
defparam \Q1[4]~I .output_power_up = "low";
defparam \Q1[4]~I .output_register_mode = "none";
defparam \Q1[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_T4
stratix_io \Q1[5]~I (
	.datain(\Q1[5]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[5]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[5]~I .ddio_mode = "none";
defparam \Q1[5]~I .input_async_reset = "none";
defparam \Q1[5]~I .input_power_up = "low";
defparam \Q1[5]~I .input_register_mode = "none";
defparam \Q1[5]~I .input_sync_reset = "none";
defparam \Q1[5]~I .oe_async_reset = "none";
defparam \Q1[5]~I .oe_power_up = "low";
defparam \Q1[5]~I .oe_register_mode = "none";
defparam \Q1[5]~I .oe_sync_reset = "none";
defparam \Q1[5]~I .operation_mode = "output";
defparam \Q1[5]~I .output_async_reset = "none";
defparam \Q1[5]~I .output_power_up = "low";
defparam \Q1[5]~I .output_register_mode = "none";
defparam \Q1[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_T3
stratix_io \Q1[6]~I (
	.datain(\Q1[6]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[6]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[6]~I .ddio_mode = "none";
defparam \Q1[6]~I .input_async_reset = "none";
defparam \Q1[6]~I .input_power_up = "low";
defparam \Q1[6]~I .input_register_mode = "none";
defparam \Q1[6]~I .input_sync_reset = "none";
defparam \Q1[6]~I .oe_async_reset = "none";
defparam \Q1[6]~I .oe_power_up = "low";
defparam \Q1[6]~I .oe_register_mode = "none";
defparam \Q1[6]~I .oe_sync_reset = "none";
defparam \Q1[6]~I .operation_mode = "output";
defparam \Q1[6]~I .output_async_reset = "none";
defparam \Q1[6]~I .output_power_up = "low";
defparam \Q1[6]~I .output_register_mode = "none";
defparam \Q1[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_V1
stratix_io \Q1[7]~I (
	.datain(\Q1[7]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[7]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[7]~I .ddio_mode = "none";
defparam \Q1[7]~I .input_async_reset = "none";
defparam \Q1[7]~I .input_power_up = "low";
defparam \Q1[7]~I .input_register_mode = "none";
defparam \Q1[7]~I .input_sync_reset = "none";
defparam \Q1[7]~I .oe_async_reset = "none";
defparam \Q1[7]~I .oe_power_up = "low";
defparam \Q1[7]~I .oe_register_mode = "none";
defparam \Q1[7]~I .oe_sync_reset = "none";
defparam \Q1[7]~I .operation_mode = "output";
defparam \Q1[7]~I .output_async_reset = "none";
defparam \Q1[7]~I .output_power_up = "low";
defparam \Q1[7]~I .output_register_mode = "none";
defparam \Q1[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_U5
stratix_io \Q1[8]~I (
	.datain(\Q1[8]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[8]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[8]~I .ddio_mode = "none";
defparam \Q1[8]~I .input_async_reset = "none";
defparam \Q1[8]~I .input_power_up = "low";
defparam \Q1[8]~I .input_register_mode = "none";
defparam \Q1[8]~I .input_sync_reset = "none";
defparam \Q1[8]~I .oe_async_reset = "none";
defparam \Q1[8]~I .oe_power_up = "low";
defparam \Q1[8]~I .oe_register_mode = "none";
defparam \Q1[8]~I .oe_sync_reset = "none";
defparam \Q1[8]~I .operation_mode = "output";
defparam \Q1[8]~I .output_async_reset = "none";
defparam \Q1[8]~I .output_power_up = "low";
defparam \Q1[8]~I .output_register_mode = "none";
defparam \Q1[8]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_R4
stratix_io \Q1[9]~I (
	.datain(\Q1[9]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[9]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[9]~I .ddio_mode = "none";
defparam \Q1[9]~I .input_async_reset = "none";
defparam \Q1[9]~I .input_power_up = "low";
defparam \Q1[9]~I .input_register_mode = "none";
defparam \Q1[9]~I .input_sync_reset = "none";
defparam \Q1[9]~I .oe_async_reset = "none";
defparam \Q1[9]~I .oe_power_up = "low";
defparam \Q1[9]~I .oe_register_mode = "none";
defparam \Q1[9]~I .oe_sync_reset = "none";
defparam \Q1[9]~I .operation_mode = "output";
defparam \Q1[9]~I .output_async_reset = "none";
defparam \Q1[9]~I .output_power_up = "low";
defparam \Q1[9]~I .output_register_mode = "none";
defparam \Q1[9]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_U1
stratix_io \Q1[10]~I (
	.datain(\Q1[10]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q1[10]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q1[10]~I .ddio_mode = "none";
defparam \Q1[10]~I .input_async_reset = "none";
defparam \Q1[10]~I .input_power_up = "low";
defparam \Q1[10]~I .input_register_mode = "none";
defparam \Q1[10]~I .input_sync_reset = "none";
defparam \Q1[10]~I .oe_async_reset = "none";
defparam \Q1[10]~I .oe_power_up = "low";
defparam \Q1[10]~I .oe_register_mode = "none";
defparam \Q1[10]~I .oe_sync_reset = "none";
defparam \Q1[10]~I .operation_mode = "output";
defparam \Q1[10]~I .output_async_reset = "none";
defparam \Q1[10]~I .output_power_up = "low";
defparam \Q1[10]~I .output_register_mode = "none";
defparam \Q1[10]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_V2
stratix_io \Q2[0]~I (
	.datain(\Q2[1]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.padio(Q2[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \Q2[0]~I .ddio_mode = "none";
defparam \Q2[0]~I .input_async_reset = "none";
defparam \Q2[0]~I .input_power_up = "low";
defparam \Q2[0]~I .input_register_mode = "none";
defparam \Q2[0]~I .input_sync_reset = "none";
defparam \Q2[0]~I .oe_async_reset = "none";
defparam \Q2[0]~I .oe_power_up = "low";
defparam \Q2[0]~I .oe_register_mode = "none";
defparam \Q2[0]~I .oe_sync_reset = "none";
defparam \Q2[0]~I .operation_mode = "output";
defparam \Q2[0]~I .output_async_reset = "none";
defparam \Q2[0]~I .output_power_up = "low";
defparam \Q2[0]~I .output_register_mode = "none";
defparam \Q2[0]~I .output_sync_reset = "none";