c_a.vo

GPS中C/A码产生简单的Verilog逻辑产生

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "02/27/2009 15:44:41"

// 
// Device: Altera EP1S10F484C5 Package FBGA484
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module c_a (
	clk,
	clr,
	Q1,
	Q2,
	G1,
	G2,
	c_a);
input 	clk;
input 	clr;
output 	[10:0] Q1;
output 	[10:0] Q2;
output 	G1;
output 	G2;
output 	c_a;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("c_a_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \clr~combout ;
wire \Q1[2]~reg0 ;
wire \Q1[3]~reg0 ;
wire \Q1[4]~reg0 ;
wire \Q1[5]~reg0 ;
wire \Q1[6]~reg0 ;
wire \Q1[7]~reg0 ;
wire \Q1[8]~reg0 ;
wire \Q1[9]~reg0 ;
wire \Q1[10]~reg0 ;
wire \Q1[1]~reg0 ;
wire \Q2[2]~reg0 ;
wire \Q2[3]~reg0 ;
wire \Q2[4]~reg0 ;
wire \Q2[5]~reg0 ;
wire \Q2[6]~reg0 ;
wire \Q2[7]~reg0 ;
wire \Q2[8]~reg0 ;
wire \Q2[9]~reg0 ;
wire \Q2[10]~reg0 ;
wire \Q2~173 ;
wire \Q2[1]~reg0 ;
wire \G1~reg0 ;
wire \G2~reg0 ;
wire \c_a~reg0 ;


// atom is at PIN_M20
stratix_io \clk~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.ddioregout(),
	.padio(clk),
	.dqsundelayedout());
// synopsys translate_off
defparam \clk~I .ddio_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_M2
stratix_io \clr~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clr~combout ),
	.regout(),
	.ddioregout(),
	.padio(clr),
	.dqsundelayedout());
// synopsys translate_off
defparam \clr~I .ddio_mode = "none";
defparam \clr~I .input_async_reset = "none";
defparam \clr~I .input_power_up = "low";
defparam \clr~I .input_register_mode = "none";
defparam \clr~I .input_sync_reset = "none";
defparam \clr~I .oe_async_reset = "none";
defparam \clr~I .oe_power_up = "low";
defparam \clr~I .oe_register_mode = "none";
defparam \clr~I .oe_sync_reset = "none";
defparam \clr~I .operation_mode = "input";
defparam \clr~I .output_async_reset = "none";
defparam \clr~I .output_power_up = "low";
defparam \clr~I .output_register_mode = "none";
defparam \clr~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X52_Y7_N8
stratix_lcell \Q1[2]~reg0_I (
// Equation(s):
// \Q1[2]~reg0  = DFFEAS(\Q1[1]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Q1[1]~reg0 ),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[2]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[2]~reg0_I .lut_mask = "F0FF";
defparam \Q1[2]~reg0_I .operation_mode = "normal";
defparam \Q1[2]~reg0_I .output_mode = "reg_only";
defparam \Q1[2]~reg0_I .register_cascade_mode = "off";
defparam \Q1[2]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[2]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N9
stratix_lcell \Q1[3]~reg0_I (
// Equation(s):
// \Q1[3]~reg0  = DFFEAS(\Q1[2]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(\Q1[2]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[3]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[3]~reg0_I .lut_mask = "AAFF";
defparam \Q1[3]~reg0_I .operation_mode = "normal";
defparam \Q1[3]~reg0_I .output_mode = "reg_only";
defparam \Q1[3]~reg0_I .register_cascade_mode = "off";
defparam \Q1[3]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[3]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N6
stratix_lcell \Q1[4]~reg0_I (
// Equation(s):
// \Q1[4]~reg0  = DFFEAS(\Q1[3]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\Q1[3]~reg0 ),
	.datac(vcc),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[4]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[4]~reg0_I .lut_mask = "CCFF";
defparam \Q1[4]~reg0_I .operation_mode = "normal";
defparam \Q1[4]~reg0_I .output_mode = "reg_only";
defparam \Q1[4]~reg0_I .register_cascade_mode = "off";
defparam \Q1[4]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[4]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N2
stratix_lcell \Q1[5]~reg0_I (
// Equation(s):
// \Q1[5]~reg0  = DFFEAS(\Q1[4]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\Q1[4]~reg0 ),
	.datac(vcc),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[5]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[5]~reg0_I .lut_mask = "CCFF";
defparam \Q1[5]~reg0_I .operation_mode = "normal";
defparam \Q1[5]~reg0_I .output_mode = "reg_only";
defparam \Q1[5]~reg0_I .register_cascade_mode = "off";
defparam \Q1[5]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[5]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N3
stratix_lcell \Q1[6]~reg0_I (
// Equation(s):
// \Q1[6]~reg0  = DFFEAS(\Q1[5]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(\Q1[5]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[6]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[6]~reg0_I .lut_mask = "AAFF";
defparam \Q1[6]~reg0_I .operation_mode = "normal";
defparam \Q1[6]~reg0_I .output_mode = "reg_only";
defparam \Q1[6]~reg0_I .register_cascade_mode = "off";
defparam \Q1[6]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[6]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N5
stratix_lcell \Q1[7]~reg0_I (
// Equation(s):
// \Q1[7]~reg0  = DFFEAS(\Q1[6]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Q1[6]~reg0 ),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[7]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[7]~reg0_I .lut_mask = "F0FF";
defparam \Q1[7]~reg0_I .operation_mode = "normal";
defparam \Q1[7]~reg0_I .output_mode = "reg_only";
defparam \Q1[7]~reg0_I .register_cascade_mode = "off";
defparam \Q1[7]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[7]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N0
stratix_lcell \Q1[8]~reg0_I (
// Equation(s):
// \Q1[8]~reg0  = DFFEAS(\Q1[7]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Q1[7]~reg0 ),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[8]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[8]~reg0_I .lut_mask = "F0FF";
defparam \Q1[8]~reg0_I .operation_mode = "normal";
defparam \Q1[8]~reg0_I .output_mode = "reg_only";
defparam \Q1[8]~reg0_I .register_cascade_mode = "off";
defparam \Q1[8]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[8]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N7
stratix_lcell \Q1[9]~reg0_I (
// Equation(s):
// \Q1[9]~reg0  = DFFEAS(\Q1[8]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\Q1[8]~reg0 ),
	.datac(vcc),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[9]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[9]~reg0_I .lut_mask = "CCFF";
defparam \Q1[9]~reg0_I .operation_mode = "normal";
defparam \Q1[9]~reg0_I .output_mode = "reg_only";
defparam \Q1[9]~reg0_I .register_cascade_mode = "off";
defparam \Q1[9]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[9]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N4
stratix_lcell \Q1[10]~reg0_I (
// Equation(s):
// \Q1[10]~reg0  = DFFEAS(\Q1[9]~reg0  # !\clr~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Q1[9]~reg0 ),
	.datad(\clr~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Q1[10]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Q1[10]~reg0_I .lut_mask = "F0FF";
defparam \Q1[10]~reg0_I .operation_mode = "normal";
defparam \Q1[10]~reg0_I .output_mode = "reg_only";
defparam \Q1[10]~reg0_I .register_cascade_mode = "off";
defparam \Q1[10]~reg0_I .sum_lutc_input = "datac";
defparam \Q1[10]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X52_Y7_N1
stratix_lcell \Q1[1]~reg0_I (
// Equation(s):
// \Q1[1]~reg0  = DFFEAS(\Q1[10]~reg0  $ \Q1[3]~reg0  $ A1L8Q $ \Q1[4]~reg0 , GLOBAL(\clk~combout ), VCC, , , VCC, , , !\clr~combout )

	.clk(\clk~combout ),