first.vhd

来自「spartan3adsp spi flash」· VHDL 代码 · 共 47 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity blinky1 is
    Port ( LED               : out STD_LOGIC_VECTOR (7 downto 0);
			  CLOCK_125MHZ      : in  STD_LOGIC
			 );
end blinky1;

architecture Behavioral of blinky1 is

-- Create a 24-bit timer to divide the 50 MHz clock input by 16M.
-- This slows the clock to a human friendly level
signal CLOCK_TIMER : STD_LOGIC_VECTOR (24 downto 0):= "0000000000000000000000000" ;

-- Create a "rotator" to blink the LEDs in a certain sequence
signal LED_ROTATE  : STD_LOGIC_VECTOR (7 downto 0) := "00000001" ;

begin

   -- The right eight LEDs on the board display the rotating pattern
	LED (7 downto 0) <= LED_ROTATE;
		
process (CLOCK_125MHZ)
	begin
	
	if rising_edge (CLOCK_125MHZ) then
	
		-- Increment clock timer
		CLOCK_TIMER <= CLOCK_TIMER + 1 ;
		
		-- When timer reaches maximum value, rotate LEDs
		if (CLOCK_TIMER = "1111111111111111111111111") then 
			LED_ROTATE <= LED_ROTATE(6 downto 0) & LED_ROTATE(7) ;
		end if ;
	end if ;
	
end process;


end Behavioral;