ltout.rpt
来自「用PLC程序编写十字路口的交通灯」· RPT 代码 · 共 727 行 · 第 1/2 页
RPT
727 行
Project Information c:\rgy\ltout.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 01/05/2004 11:45:06
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
LTOUT
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
ltout EPF10K10LC84-4 24 22 0 0 0 % 22 3 %
User Pins: 24 22 0
Project Information c:\rgy\ltout.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
ltout@19 ag
ltout@27 al
ltout@22 ar
ltout@51 atime0
ltout@52 atime1
ltout@53 atime2
ltout@54 atime3
ltout@58 atime4
ltout@59 atime5
ltout@60 atime6
ltout@21 ay
ltout@16 bg
ltout@23 bl
ltout@18 br
ltout@61 btime0
ltout@62 btime1
ltout@64 btime2
ltout@65 btime3
ltout@66 btime4
ltout@70 btime6
ltout@17 by
Device-Specific Information: c:\rgy\ltout.rpt
ltout
***** Logic for device 'ltout' compiled without errors.
Device: EPF10K10LC84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R R O
E E E E E E E E E N
S S S S S S S V S S G b F
E E E E E E E C E E N t _ ^
R R R R R R R C R R D i # D n
V V V V V V V I V t t V I m t t b T O C
E E E E E E E N E e b b E N e a a l C N E
D D D D D D D T D n 2 1 D T 5 3 2 0 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | tb4
^nCE | 14 72 | tb6
#TDI | 15 71 | bg0
bg | 16 70 | btime6
by | 17 69 | ta4
br | 18 68 | GNDINT
ag | 19 67 | ta5
VCCINT | 20 66 | btime4
ay | 21 65 | btime3
ar | 22 EPF10K10LC84-4 64 | btime2
bl | 23 63 | VCCINT
ay0 | 24 62 | btime1
by0 | 25 61 | btime0
GNDINT | 26 60 | atime6
al | 27 59 | atime5
ta6 | 28 58 | atime4
ar0 | 29 57 | #TMS
tb5 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | atime3
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R a R R b V G c t t V G t a R t a a a
C n E l E E r C N l b b C N a g E a t t t
C C S 0 S S 0 C D k 3 0 C D 0 0 S 1 i i i
I O E E E I I I I E m m m
N N R R R N N N N R e e e
T F V V V T T T T V 0 1 2
I E E E E
G D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\rgy\ltout.rpt
ltout
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A18 5/ 8( 62%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
B20 7/ 8( 87%) 5/ 8( 62%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
C4 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C21 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 40/53 ( 75%)
Total logic cells used: 22/576 ( 3%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.63/4 ( 65%)
Total fan-in: 58/2304 ( 2%)
Total input pins required: 24
Total input I/O cell registers required: 0
Total output pins required: 22
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 22
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 5/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 7/0
C: 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 10/0
Total: 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 7 8 0 0 0 22/0
Device-Specific Information: c:\rgy\ltout.rpt
ltout
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
48 - - - 15 INPUT 0 0 0 1 ag0
36 - - - 07 INPUT 0 0 0 1 al0
29 - - C -- INPUT 0 0 0 1 ar0
24 - - B -- INPUT 0 0 0 1 ay0
71 - - A -- INPUT 0 0 0 1 bg0
78 - - - 24 INPUT 0 0 0 1 bl0
39 - - - 11 INPUT 0 0 0 1 br0
25 - - B -- INPUT 0 0 0 1 by0
42 - - - -- INPUT 0 0 0 14 clk
2 - - - -- INPUT 0 0 0 22 en
47 - - - 14 INPUT 0 0 0 1 ta0
50 - - - 17 INPUT 0 0 0 1 ta1
79 - - - 24 INPUT 0 0 0 1 ta2
80 - - - 23 INPUT 0 0 0 1 ta3
69 - - A -- INPUT 0 0 0 1 ta4
67 - - B -- INPUT 0 0 0 1 ta5
28 - - C -- INPUT 0 0 0 1 ta6
44 - - - -- INPUT 0 0 0 1 tb0
84 - - - -- INPUT 0 0 0 1 tb1
1 - - - -- INPUT 0 0 0 1 tb2
43 - - - -- INPUT 0 0 0 1 tb3
73 - - A -- INPUT 0 0 0 1 tb4
30 - - C -- INPUT 0 0 0 1 tb5
72 - - A -- INPUT 0 0 0 1 tb6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\rgy\ltout.rpt
ltout
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- OUTPUT 0 1 0 0 ag
27 - - C -- OUTPUT 0 1 0 0 al
22 - - B -- OUTPUT 0 1 0 0 ar
51 - - - 18 OUTPUT 0 1 0 0 atime0
52 - - - 19 OUTPUT 0 1 0 0 atime1
53 - - - 20 OUTPUT 0 1 0 0 atime2
54 - - - 21 OUTPUT 0 1 0 0 atime3
58 - - C -- OUTPUT 0 1 0 0 atime4
59 - - C -- OUTPUT 0 1 0 0 atime5
60 - - C -- OUTPUT 0 1 0 0 atime6
21 - - B -- OUTPUT 0 1 0 0 ay
16 - - A -- OUTPUT 0 1 0 0 bg
23 - - B -- OUTPUT 0 1 0 0 bl
18 - - A -- OUTPUT 0 1 0 0 br
61 - - C -- OUTPUT 0 1 0 0 btime0
62 - - C -- OUTPUT 0 1 0 0 btime1
64 - - B -- OUTPUT 0 1 0 0 btime2
65 - - B -- OUTPUT 0 1 0 0 btime3
66 - - B -- OUTPUT 0 1 0 0 btime4
81 - - - 22 OUTPUT 0 1 0 0 btime5
70 - - A -- OUTPUT 0 1 0 0 btime6
17 - - A -- OUTPUT 0 1 0 0 by
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\rgy\ltout.rpt
ltout
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 21 OR2 2 0 1 0 :47
- 6 - B 20 AND2 2 0 1 0 :50
- 1 - B 20 AND2 2 0 1 0 :53
- 1 - C 04 AND2 2 0 1 0 :56
- 5 - C 04 OR2 2 0 1 0 :57
- 1 - A 18 AND2 2 0 1 0 :60
- 3 - B 20 AND2 2 0 1 0 :63
- 4 - B 20 AND2 2 0 1 0 :66
- 4 - C 21 OR2 3 0 1 0 :146
- 5 - B 20 OR2 3 0 1 0 :152
- 6 - A 18 OR2 3 0 1 0 :158
- 6 - C 21 OR2 3 0 1 0 :164
- 2 - B 20 OR2 3 0 1 0 :170
- 7 - B 20 OR2 3 0 1 0 :176
- 3 - A 18 OR2 3 0 1 0 :182
- 5 - A 18 OR2 3 0 1 0 :264
- 8 - C 21 OR2 3 0 1 0 :270
- 2 - A 18 OR2 3 0 1 0 :276
- 5 - C 21 OR2 3 0 1 0 :282
- 7 - C 21 OR2 3 0 1 0 :288
- 1 - C 21 OR2 3 0 1 0 :294
- 3 - C 21 OR2 3 0 1 0 :300
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\rgy\ltout.rpt
ltout
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 1/ 48( 2%) 1/ 48( 2%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 6/ 96( 6%) 0/ 48( 0%) 7/ 48( 14%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 3/ 96( 3%) 3/ 48( 6%) 6/ 48( 12%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?