ltout.rpt
来自「用PLC程序编写十字路口的交通灯」· RPT 代码 · 共 727 行 · 第 1/2 页
RPT
727 行
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16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
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23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\rgy\ltout.rpt
ltout
** EQUATIONS **
ag0 : INPUT;
al0 : INPUT;
ar0 : INPUT;
ay0 : INPUT;
bg0 : INPUT;
bl0 : INPUT;
br0 : INPUT;
by0 : INPUT;
clk : INPUT;
en : INPUT;
ta0 : INPUT;
ta1 : INPUT;
ta2 : INPUT;
ta3 : INPUT;
ta4 : INPUT;
ta5 : INPUT;
ta6 : INPUT;
tb0 : INPUT;
tb1 : INPUT;
tb2 : INPUT;
tb3 : INPUT;
tb4 : INPUT;
tb5 : INPUT;
tb6 : INPUT;
-- Node name is 'ag'
-- Equation name is 'ag', type is output
ag = _LC6_B20;
-- Node name is 'al'
-- Equation name is 'al', type is output
al = _LC1_C4;
-- Node name is 'ar'
-- Equation name is 'ar', type is output
ar = _LC2_C21;
-- Node name is 'atime0'
-- Equation name is 'atime0', type is output
atime0 = _LC3_A18;
-- Node name is 'atime1'
-- Equation name is 'atime1', type is output
atime1 = _LC7_B20;
-- Node name is 'atime2'
-- Equation name is 'atime2', type is output
atime2 = _LC2_B20;
-- Node name is 'atime3'
-- Equation name is 'atime3', type is output
atime3 = _LC6_C21;
-- Node name is 'atime4'
-- Equation name is 'atime4', type is output
atime4 = _LC6_A18;
-- Node name is 'atime5'
-- Equation name is 'atime5', type is output
atime5 = _LC5_B20;
-- Node name is 'atime6'
-- Equation name is 'atime6', type is output
atime6 = _LC4_C21;
-- Node name is 'ay'
-- Equation name is 'ay', type is output
ay = _LC1_B20;
-- Node name is 'bg'
-- Equation name is 'bg', type is output
bg = _LC1_A18;
-- Node name is 'bl'
-- Equation name is 'bl', type is output
bl = _LC4_B20;
-- Node name is 'br'
-- Equation name is 'br', type is output
br = _LC5_C4;
-- Node name is 'btime0'
-- Equation name is 'btime0', type is output
btime0 = _LC3_C21;
-- Node name is 'btime1'
-- Equation name is 'btime1', type is output
btime1 = _LC1_C21;
-- Node name is 'btime2'
-- Equation name is 'btime2', type is output
btime2 = _LC7_C21;
-- Node name is 'btime3'
-- Equation name is 'btime3', type is output
btime3 = _LC5_C21;
-- Node name is 'btime4'
-- Equation name is 'btime4', type is output
btime4 = _LC2_A18;
-- Node name is 'btime5'
-- Equation name is 'btime5', type is output
btime5 = _LC8_C21;
-- Node name is 'btime6'
-- Equation name is 'btime6', type is output
btime6 = _LC5_A18;
-- Node name is 'by'
-- Equation name is 'by', type is output
by = _LC3_B20;
-- Node name is ':47'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ001);
_EQ001 = ar0
# en;
-- Node name is ':50'
-- Equation name is '_LC6_B20', type is buried
_LC6_B20 = LCELL( _EQ002);
_EQ002 = ag0 & !en;
-- Node name is ':53'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _EQ003);
_EQ003 = ay0 & !en;
-- Node name is ':56'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ004);
_EQ004 = al0 & !en;
-- Node name is ':57'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = LCELL( _EQ005);
_EQ005 = br0
# en;
-- Node name is ':60'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ006);
_EQ006 = bg0 & !en;
-- Node name is ':63'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ007);
_EQ007 = by0 & !en;
-- Node name is ':66'
-- Equation name is '_LC4_B20', type is buried
_LC4_B20 = LCELL( _EQ008);
_EQ008 = bl0 & !en;
-- Node name is ':146'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = LCELL( _EQ009);
_EQ009 = !en & ta6
# clk & ta6;
-- Node name is ':152'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = LCELL( _EQ010);
_EQ010 = !en & ta5
# clk & ta5;
-- Node name is ':158'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = LCELL( _EQ011);
_EQ011 = !en & ta4
# clk & ta4;
-- Node name is ':164'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ012);
_EQ012 = !en & ta3
# clk & ta3;
-- Node name is ':170'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ013);
_EQ013 = !en & ta2
# clk & ta2;
-- Node name is ':176'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = LCELL( _EQ014);
_EQ014 = !en & ta1
# clk & ta1;
-- Node name is ':182'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = LCELL( _EQ015);
_EQ015 = !en & ta0
# clk & ta0;
-- Node name is ':264'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ016);
_EQ016 = !en & tb6
# clk & tb6;
-- Node name is ':270'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ017);
_EQ017 = !en & tb5
# clk & tb5;
-- Node name is ':276'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = LCELL( _EQ018);
_EQ018 = !en & tb4
# clk & tb4;
-- Node name is ':282'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = LCELL( _EQ019);
_EQ019 = !en & tb3
# clk & tb3;
-- Node name is ':288'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ020);
_EQ020 = !en & tb2
# clk & tb2;
-- Node name is ':294'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ021);
_EQ021 = !en & tb1
# clk & tb1;
-- Node name is ':300'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = LCELL( _EQ022);
_EQ022 = !en & tb0
# clk & tb0;
Project Information c:\rgy\ltout.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,103K
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