fifo.tan.rpt

FIFO yibu de v daima

; Clock Setup: 'clk_rd'        ; N/A   ; None          ; 134.03 MHz ( period = 7.461 ns ) ; FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] ; FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[7]                                                     ; clk_rd     ; clk_rd   ; 0            ;
; Clock Setup: 'clk_wr'        ; N/A   ; None          ; 145.31 MHz ( period = 6.882 ns ) ; FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[6] ; FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[7]                                                     ; clk_wr     ; clk_wr   ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                           ;                                                                                                               ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_rd          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk_wr          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_rd'                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+