prev_cmp_fifo.tan.qmsg

来自「FIFO yibu de v daima」· QMSG 代码 · 共 23 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\] rst clk_rd 8.699 ns register " "Info: tsu for register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]\" (data pin = \"rst\", clock pin = \"clk_rd\") is 8.699 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.616 ns + Longest pin register " "Info: + Longest pin to register delay is 11.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_38 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 2; PIN Node = 'rst'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.014 ns) + CELL(0.292 ns) 9.775 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|always0~63 2 COMB LC_X13_Y15_N1 8 " "Info: 2: + IC(8.014 ns) + CELL(0.292 ns) = 9.775 ns; Loc. = LC_X13_Y15_N1; Fanout = 8; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|always0~63'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.306 ns" { rst FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(1.112 ns) 11.616 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\] 3 REG LC_X14_Y15_N3 10 " "Info: 3: + IC(0.729 ns) + CELL(1.112 ns) = 11.616 ns; Loc. = LC_X14_Y15_N3; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.841 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.873 ns ( 24.73 % ) " "Info: Total cell delay = 2.873 ns ( 24.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.743 ns ( 75.27 % ) " "Info: Total interconnect delay = 8.743 ns ( 75.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.616 ns" { rst FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.616 ns" { rst {} rst~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 8.014ns 0.729ns } { 0.000ns 1.469ns 0.292ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_rd destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_rd\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_rd 1 CLK PIN_28 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 23; CLK Node = 'clk_rd'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_rd } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\] 2 REG LC_X14_Y15_N3 10 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N3; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.616 ns" { rst FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.616 ns" { rst {} rst~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|always0~63 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 8.014ns 0.729ns } { 0.000ns 1.469ns 0.292ns 1.112ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_wr full FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\] 11.995 ns register " "Info: tco from clock \"clk_wr\" to destination pin \"full\" through register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]\" is 11.995 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_wr source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk_wr\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_wr 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clk_wr'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_wr } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\] 2 REG LC_X12_Y15_N3 12 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y15_N3; Fanout = 12; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_wr {} clk_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.817 ns + Longest register pin " "Info: + Longest register to pin delay is 8.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\] 1 REG LC_X12_Y15_N3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y15_N3; Fanout = 12; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.292 ns) 1.542 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~376 2 COMB LC_X15_Y15_N9 1 " "Info: 2: + IC(1.250 ns) + CELL(0.292 ns) = 1.542 ns; Loc. = LC_X15_Y15_N9; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~376'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 2.559 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~377 3 COMB LC_X15_Y15_N4 2 " "Info: 3: + IC(0.427 ns) + CELL(0.590 ns) = 2.559 ns; Loc. = LC_X15_Y15_N4; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~377'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.017 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.292 ns) 3.999 ns FIFO_ctl:FIFO_ctl_inst\|full 4 COMB LC_X12_Y15_N8 19 " "Info: 4: + IC(1.148 ns) + CELL(0.292 ns) = 3.999 ns; Loc. = LC_X12_Y15_N8; Fanout = 19; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|full'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|full } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.710 ns) + CELL(2.108 ns) 8.817 ns full 5 PIN PIN_82 0 " "Info: 5: + IC(2.710 ns) + CELL(2.108 ns) = 8.817 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'full'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.818 ns" { FIFO_ctl:FIFO_ctl_inst|full full } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.282 ns ( 37.22 % ) " "Info: Total cell delay = 3.282 ns ( 37.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.535 ns ( 62.78 % ) " "Info: Total interconnect delay = 5.535 ns ( 62.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.817 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|full full } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.817 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} FIFO_ctl:FIFO_ctl_inst|Equal1~376 {} FIFO_ctl:FIFO_ctl_inst|Equal1~377 {} FIFO_ctl:FIFO_ctl_inst|full {} full {} } { 0.000ns 1.250ns 0.427ns 1.148ns 2.710ns } { 0.000ns 0.292ns 0.590ns 0.292ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_wr {} clk_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.817 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|full full } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.817 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} FIFO_ctl:FIFO_ctl_inst|Equal1~376 {} FIFO_ctl:FIFO_ctl_inst|Equal1~377 {} FIFO_ctl:FIFO_ctl_inst|full {} full {} } { 0.000ns 1.250ns 0.427ns 1.148ns 2.710ns } { 0.000ns 0.292ns 0.590ns 0.292ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_datain_reg2 data_in\[2\] clk_wr -4.810 ns memory " "Info: th for memory \"Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_datain_reg2\" (data pin = \"data_in\[2\]\", clock pin = \"clk_wr\") is -4.810 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_wr destination 2.973 ns + Longest memory " "Info: + Longest clock path from clock \"clk_wr\" to destination memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_wr 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clk_wr'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_wr } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.722 ns) 2.973 ns Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_datain_reg2 2 MEM M4K_X17_Y16 1 " "Info: 2: + IC(0.782 ns) + CELL(0.722 ns) = 2.973 ns; Loc. = M4K_X17_Y16; Fanout = 1; MEM Node = 'Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_datain_reg2'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } } { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 73.70 % ) " "Info: Total cell delay = 2.191 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk_wr {} clk_wr~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" {  } { { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.838 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 7.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns data_in\[2\] 1 PIN PIN_215 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_215; Fanout = 1; PIN Node = 'data_in\[2\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in[2] } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.007 ns) + CELL(0.356 ns) 7.838 ns Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_datain_reg2 2 MEM M4K_X17_Y16 1 " "Info: 2: + IC(6.007 ns) + CELL(0.356 ns) = 7.838 ns; Loc. = M4K_X17_Y16; Fanout = 1; MEM Node = 'Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_datain_reg2'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.363 ns" { data_in[2] Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } } { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.831 ns ( 23.36 % ) " "Info: Total cell delay = 1.831 ns ( 23.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.007 ns ( 76.64 % ) " "Info: Total interconnect delay = 6.007 ns ( 76.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.838 ns" { data_in[2] Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.838 ns" { data_in[2] {} data_in[2]~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 {} } { 0.000ns 0.000ns 6.007ns } { 0.000ns 1.475ns 0.356ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk_wr {} clk_wr~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.838 ns" { data_in[2] Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.838 ns" { data_in[2] {} data_in[2]~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_datain_reg2 {} } { 0.000ns 0.000ns 6.007ns } { 0.000ns 1.475ns 0.356ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0