prev_cmp_fifo.tan.qmsg

来自「FIFO yibu de v daima」· QMSG 代码 · 共 23 行 · 第 1/5 页

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "FIFO_ctl:FIFO_ctl_inst\|G2B:G2B_wr\|Bin~5 " "Warning: Node \"FIFO_ctl:FIFO_ctl_inst\|G2B:G2B_wr\|Bin~5\"" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 3 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 0}  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 3 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "FIFO_ctl:FIFO_ctl_inst\|G2B:G2B_wr\|Bin~6 " "Warning: Node \"FIFO_ctl:FIFO_ctl_inst\|G2B:G2B_wr\|Bin~6\"" {  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 3 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0 0}  } { { "G2B.v" "" { Text "E:/FIFO_yibu/G2B.v" 3 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_rd " "Info: Assuming node \"clk_rd\" is an undefined clock" {  } { { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 2 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_rd" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_wr " "Info: Assuming node \"clk_wr\" is an undefined clock" {  } { { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 1 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_wr" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_rd register FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\] register FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 150.42 MHz 6.648 ns Internal " "Info: Clock \"clk_rd\" has Internal fmax of 150.42 MHz between source register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]\" and destination register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]\" (period= 6.648 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.387 ns + Longest register register " "Info: + Longest register to register delay is 6.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\] 1 REG LC_X14_Y15_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y15_N3; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.590 ns) 1.396 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~376 2 COMB LC_X15_Y15_N9 1 " "Info: 2: + IC(0.806 ns) + CELL(0.590 ns) = 1.396 ns; Loc. = LC_X15_Y15_N9; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~376'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.396 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 2.413 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~377 3 COMB LC_X15_Y15_N4 2 " "Info: 3: + IC(0.427 ns) + CELL(0.590 ns) = 2.413 ns; Loc. = LC_X15_Y15_N4; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~377'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.017 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.442 ns) 3.557 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~378 4 COMB LC_X14_Y15_N9 2 " "Info: 4: + IC(0.702 ns) + CELL(0.442 ns) = 3.557 ns; Loc. = LC_X14_Y15_N9; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~378'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.144 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|Equal1~378 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.292 ns) 4.303 ns FIFO_ctl:FIFO_ctl_inst\|rd_en~13 5 COMB LC_X14_Y15_N8 3 " "Info: 5: + IC(0.454 ns) + CELL(0.292 ns) = 4.303 ns; Loc. = LC_X14_Y15_N8; Fanout = 3; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|rd_en~13'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.746 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~378 FIFO_ctl:FIFO_ctl_inst|rd_en~13 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.423 ns) 5.136 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[0\]~91 6 COMB LC_X14_Y15_N0 2 " "Info: 6: + IC(0.410 ns) + CELL(0.423 ns) = 5.136 ns; Loc. = LC_X14_Y15_N0; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[0\]~91'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.833 ns" { FIFO_ctl:FIFO_ctl_inst|rd_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 5.214 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[1\]~93 7 COMB LC_X14_Y15_N1 2 " "Info: 7: + IC(0.000 ns) + CELL(0.078 ns) = 5.214 ns; Loc. = LC_X14_Y15_N1; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[1\]~93'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 5.292 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[2\]~97 8 COMB LC_X14_Y15_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.078 ns) = 5.292 ns; Loc. = LC_X14_Y15_N2; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[2\]~97'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~97 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 5.370 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]~83 9 COMB LC_X14_Y15_N3 2 " "Info: 9: + IC(0.000 ns) + CELL(0.078 ns) = 5.370 ns; Loc. = LC_X14_Y15_N3; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]~83'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~97 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~83 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 5.548 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[4\]~85 10 COMB LC_X14_Y15_N4 3 " "Info: 10: + IC(0.000 ns) + CELL(0.178 ns) = 5.548 ns; Loc. = LC_X14_Y15_N4; Fanout = 3; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[4\]~85'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~85 } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 6.387 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 11 REG LC_X14_Y15_N5 10 " "Info: 11: + IC(0.000 ns) + CELL(0.839 ns) = 6.387 ns; Loc. = LC_X14_Y15_N5; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~85 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.588 ns ( 56.18 % ) " "Info: Total cell delay = 3.588 ns ( 56.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.799 ns ( 43.82 % ) " "Info: Total interconnect delay = 2.799 ns ( 43.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.387 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|Equal1~378 FIFO_ctl:FIFO_ctl_inst|rd_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~97 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~85 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.387 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} FIFO_ctl:FIFO_ctl_inst|Equal1~376 {} FIFO_ctl:FIFO_ctl_inst|Equal1~377 {} FIFO_ctl:FIFO_ctl_inst|Equal1~378 {} FIFO_ctl:FIFO_ctl_inst|rd_en~13 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~97 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~83 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~85 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.806ns 0.427ns 0.702ns 0.454ns 0.410ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.292ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_rd destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_rd\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_rd 1 CLK PIN_28 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 23; CLK Node = 'clk_rd'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_rd } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\] 2 REG LC_X14_Y15_N5 10 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N5; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_rd source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk_rd\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_rd 1 CLK PIN_28 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 23; CLK Node = 'clk_rd'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_rd } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\] 2 REG LC_X14_Y15_N3 10 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N3; Fanout = 10; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_rd\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.387 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|Equal1~378 FIFO_ctl:FIFO_ctl_inst|rd_en~13 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~97 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~83 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~85 FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.387 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} FIFO_ctl:FIFO_ctl_inst|Equal1~376 {} FIFO_ctl:FIFO_ctl_inst|Equal1~377 {} FIFO_ctl:FIFO_ctl_inst|Equal1~378 {} FIFO_ctl:FIFO_ctl_inst|rd_en~13 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[0]~91 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[1]~93 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[2]~97 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3]~83 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[4]~85 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.806ns 0.427ns 0.702ns 0.454ns 0.410ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.292ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_rd FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_rd {} clk_rd~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_rd|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_wr register FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\] memory Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_we_reg 139.28 MHz 7.18 ns Internal " "Info: Clock \"clk_wr\" has Internal fmax of 139.28 MHz between source register \"FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]\" and destination memory \"Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_we_reg\" (period= 7.18 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.882 ns + Longest register memory " "Info: + Longest register to memory delay is 6.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\] 1 REG LC_X12_Y15_N3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y15_N3; Fanout = 12; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.292 ns) 1.542 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~376 2 COMB LC_X15_Y15_N9 1 " "Info: 2: + IC(1.250 ns) + CELL(0.292 ns) = 1.542 ns; Loc. = LC_X15_Y15_N9; Fanout = 1; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~376'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.590 ns) 2.559 ns FIFO_ctl:FIFO_ctl_inst\|Equal1~377 3 COMB LC_X15_Y15_N4 2 " "Info: 3: + IC(0.427 ns) + CELL(0.590 ns) = 2.559 ns; Loc. = LC_X15_Y15_N4; Fanout = 2; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|Equal1~377'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.017 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.292 ns) 3.999 ns FIFO_ctl:FIFO_ctl_inst\|full 4 COMB LC_X12_Y15_N8 19 " "Info: 4: + IC(1.148 ns) + CELL(0.292 ns) = 3.999 ns; Loc. = LC_X12_Y15_N8; Fanout = 19; COMB Node = 'FIFO_ctl:FIFO_ctl_inst\|full'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|full } "NODE_NAME" } } { "FIFO_ctl.v" "" { Text "E:/FIFO_yibu/FIFO_ctl.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.918 ns) + CELL(0.965 ns) 6.882 ns Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_we_reg 5 MEM M4K_X17_Y16 0 " "Info: 5: + IC(1.918 ns) + CELL(0.965 ns) = 6.882 ns; Loc. = M4K_X17_Y16; Fanout = 0; MEM Node = 'Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.883 ns" { FIFO_ctl:FIFO_ctl_inst|full Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.139 ns ( 31.08 % ) " "Info: Total cell delay = 2.139 ns ( 31.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.743 ns ( 68.92 % ) " "Info: Total interconnect delay = 4.743 ns ( 68.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.882 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|full Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.882 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} FIFO_ctl:FIFO_ctl_inst|Equal1~376 {} FIFO_ctl:FIFO_ctl_inst|Equal1~377 {} FIFO_ctl:FIFO_ctl_inst|full {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 1.250ns 0.427ns 1.148ns 1.918ns } { 0.000ns 0.292ns 0.590ns 0.292ns 0.965ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.019 ns - Smallest " "Info: - Smallest clock skew is 0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_wr destination 2.973 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_wr\" to destination memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_wr 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clk_wr'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_wr } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.722 ns) 2.973 ns Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_we_reg 2 MEM M4K_X17_Y16 0 " "Info: 2: + IC(0.782 ns) + CELL(0.722 ns) = 2.973 ns; Loc. = M4K_X17_Y16; Fanout = 0; MEM Node = 'Ram_128:Ram_128\|altsyncram:altsyncram_component\|altsyncram_sig1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 73.70 % ) " "Info: Total cell delay = 2.191 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk_wr {} clk_wr~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_wr source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk_wr\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_wr 1 CLK PIN_29 40 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 40; CLK Node = 'clk_wr'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_wr } "NODE_NAME" } } { "FIFO.v" "" { Text "E:/FIFO_yibu/FIFO.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\] 2 REG LC_X12_Y15_N3 12 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y15_N3; Fanout = 12; REG Node = 'FIFO_ctl:FIFO_ctl_inst\|gray_gena:gray_gena_inst_wr\|bin\[3\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_wr {} clk_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk_wr {} clk_wr~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_wr {} clk_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "gray_gena.v" "" { Text "E:/FIFO_yibu/gray_gena.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_sig1.tdf" "" { Text "E:/FIFO_yibu/db/altsyncram_sig1.tdf" 38 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.882 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] FIFO_ctl:FIFO_ctl_inst|Equal1~376 FIFO_ctl:FIFO_ctl_inst|Equal1~377 FIFO_ctl:FIFO_ctl_inst|full Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.882 ns" { FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} FIFO_ctl:FIFO_ctl_inst|Equal1~376 {} FIFO_ctl:FIFO_ctl_inst|Equal1~377 {} FIFO_ctl:FIFO_ctl_inst|full {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 1.250ns 0.427ns 1.148ns 1.918ns } { 0.000ns 0.292ns 0.590ns 0.292ns 0.965ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.973 ns" { clk_wr Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.973 ns" { clk_wr {} clk_wr~out0 {} Ram_128:Ram_128|altsyncram:altsyncram_component|altsyncram_sig1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk_wr FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk_wr {} clk_wr~out0 {} FIFO_ctl:FIFO_ctl_inst|gray_gena:gray_gena_inst_wr|bin[3] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}