led.vhd

led display programme

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity led is
		port(clk     :in std_logic;
			 rst_n   :in std_logic;
			 sel     :in std_logic;
			 show_a  :in std_logic_vector(31 downto 0);
			 show_b  :in std_logic_vector(31 downto 0);
			 led_ctrl:out std_logic_vector(7 downto 0);
			 led_data:out std_logic_vector(7 downto 0)
			);
end led;

architecture behave of led is
signal cnt_scan:std_logic_vector(15 downto 0);
signal data4:std_logic_vector(3 downto 0);
type state is (s_dial0,s_dial1,s_dial2,s_dial3,s_dial4,s_dial5,s_dial6,s_dial7);
signal led_state:state:=s_dial0;

component led_one 
	port(clk     :in std_logic;
		 rst_n   :in std_logic;
	     show :in std_logic_vector(3 downto 0);
	     led_data:out std_logic_vector(7 downto 0)
		);
end component;

begin
	process(clk,rst_n)
	begin
		if(rst_n='0')then cnt_scan<="0000000000000000";
		elsif clk'event and clk='1' then
				cnt_scan<=cnt_scan+"0000000000000001";
		end if;
	end process;
	
	process(cnt_scan(15),rst_n,led_state)
	begin
    if(rst_n='0')then led_ctrl <= "00000000";
    elsif (cnt_scan(15)'event and cnt_scan(15)='1') then
			case led_state is
			when s_dial0 => led_ctrl <= "01111111"; led_state <= s_dial1;
							if sel='1' then data4 <= show_a(31 downto 28);
							else data4 <= show_b(31 downto 28);
							end if;
			when s_dial1 => led_ctrl <= "10111111"; led_state <= s_dial2;
							if sel='1' then data4 <= show_a(27 downto 24);
							else data4 <= show_b(27 downto 24);
							end if;
			when s_dial2 => led_ctrl <= "11011111"; led_state <= s_dial3;
							if sel='1' then data4 <= show_a(23 downto 20);
							else data4 <= show_b(23 downto 20);
							end if;
			when s_dial3 => led_ctrl <= "11101111"; led_state <= s_dial4;
							if sel='1' then data4 <= show_a(19 downto 16);
							else data4 <= show_b(19 downto 16);
							end if;
			when s_dial4 => led_ctrl <= "11110111"; led_state <= s_dial5;
							if sel='1' then data4 <= show_a(15 downto 12);
							else data4 <= show_b(15 downto 12);
							end if;
			when s_dial5 => led_ctrl <= "11111011"; led_state <= s_dial6;
							if sel='1' then data4 <= show_a(11 downto 8);
							else data4 <= show_b(11 downto 8);
							end if;
			when s_dial6 => led_ctrl <= "11111101"; led_state <= s_dial7;
							if sel='1' then data4 <= show_a(7 downto 4);
							else data4 <= show_b(7 downto 4);
							end if;
			when s_dial7 => led_ctrl <= "11111110"; led_state <= s_dial0;
							if sel='1' then data4 <= show_a(3 downto 0);
							else data4 <= show_b(3 downto 0);
							end if;
			end case;
    end if;
	end process;
	
	U_LED:led_one port map(clk => clk,
						   rst_n => rst_n,
						   show => data4,
						   led_data => led_data
							);
end behave;