clk_div.vhd

来自「led display programme」· VHDL 代码 · 共 31 行

--clk_div.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk_div is
		port(clk    :in std_logic;--80MHz
			 rst_n  :in std_logic;
			 clk_out:out std_logic--4MHz
			);
end clk_div;

architecture behave of clk_div is
signal cout:std_logic:='0';
begin
	process(clk,rst_n)
	variable cnt:integer range 0 to 15 := 0;
	begin
		if rst_n = '0' then cnt := 0;
							cout <= '0';
			elsif clk'event and clk='1' then
					if cnt = 9 then cnt := 0;
									 cout <= not cout;
					else cnt := cnt + 1;
					end if;
		end if;
		clk_out <= cout;
	end process;
end behave;