test.vhd

This is 7-segment LED contoler in vhdl

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-- Company: 
-- Engineer:
--
-- Create Date:   00:46:17 01/10/2006
-- Design Name:   hex_display
-- Module Name:   test.vhd
-- Project Name:  dynamic_hex
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: hex_display
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT hex_display
	PORT(
		q : IN std_logic_vector(15 downto 0);
		clk : IN std_logic;          
		sel : OUT std_logic_vector(3 downto 0);
		seg : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL q :  std_logic_vector(15 downto 0) := (others=>'0');

	--Outputs
	SIGNAL sel :  std_logic_vector(3 downto 0);
	SIGNAL seg :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: hex_display PORT MAP(
		q => q,
		sel => sel,
		seg => seg,
		clk => clk
	);

	start : PROCESS	
   BEGIN
	  wait for 20 ns;
     q <= x"1234";
	  wait;
	END PROCESS; 

	tb : PROCESS
	
   BEGIN
			clk<= '1'; wait for 10 ns;
			clk<= '0'; wait for 10 ns;
	END PROCESS; 

END;