📄 cdma31.mdl
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Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Math
Operator "exp"
OutputSignalType "auto"
SampleTime "-1"
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RealImagToComplex
Input "Real and imag"
ConstantPart "0"
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Reshape
OutputDimensionality "1-D array"
OutputDimensions "[1,1]"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "CDMA31"
Location [-4, 82, 1264, 775]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [715, 137, 790, 183]
ShowName off
SourceBlock "commchan3/AWGN\nChannel"
SourceType "AWGN Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
seed "67"
noiseMode "Signal to noise ratio (Eb/No)"
EbNodB "3"
EsNodB "10"
SNRdB "100"
bitsPerSym "1"
Ps "1"
Tsym "1e-6"
variance "1"
}
Block {
BlockType Reference
Name "BPSK\nModor\nBaseband"
Ports [1, 1]
Position [255, 88, 330, 132]
ShowName off
SourceBlock "commdigbbndpm3/BPSK\nModulator\nBaseband"
SourceType "BPSK Modulator Baseband"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ph "0"
outDtype "double"
outWordLen "16"
outUDDataType "sfix(16)"
outFracLenMode "Best precision"
outFracLen "15"
}
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [150, 90, 225, 130]
ShowName off
DialogController "commDDGCreate"
DialogControllerArgs "DataTag0"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
P "0.5"
seed "61"
Ts "(1e-6)*63"
frameBased on
sampPerFrame "1"
orient off
outDataType "double"
}
Block {
BlockType Reference
Name "Cos Wave"
Ports [0, 1]
Position [335, 221, 370, 259]
SourceBlock "dspsrcs4/Sine Wave"
SourceType "Sine Wave"
Amplitude "1"
Frequency "50000"
Phase "pi/2"
SampleMode "Discrete"
OutComplex "Real"
CompMethod "Trigonometric fcn"
TableSize "Speed"
SampleTime "1e-6"
SamplesPerFrame "63"
additionalParams off
allowOverrides on
dataType "double"
wordLen "16"
udDataType "sfix(16)"
fracBitsMode "Best precision"
numFracBits "15"
ResetState "Restart at time zero"
}
Block {
BlockType Display
Name "FE"
Ports [1]
Position [960, 145, 1050, 175]
BackgroundColor "lightBlue"
Decimation "1"
Lockdown off
}
Block {
BlockType Reference
Name "Multipath Rayleigh\nFading Channel"
Ports [1, 1]
Position [595, 133, 680, 187]
ShowName off
SourceBlock "commchan3/Multipath Rayleigh\nFading Channel"
SourceType "Multipath Rayleigh Fading Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
maxDopplerShift "40"
pathDelays "[0 1e-6 2e-6]"
avgPathGaindB "[0 -1 -9]"
normalizePathGains on
seed "73"
enableProbe "0"
openVisAtStart off
outPathGains off
outDelay off
}
Block {
BlockType Reference
Name "PN Sequence1"
Ports [0, 1]
Position [150, 165, 225, 205]
ShowName off
SourceBlock "commseqgen2/PN Sequence\nGenerator"
SourceType "PN Sequence Generator"
poly "[6 5 0]"
ini_sta "[0 0 1 0 0 1]"
shift "0"
Ts "1e-6"
frameBased on
sampPerFrame "63"
reset off
outDataType "double"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [390, 132, 420, 163]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [505, 142, 535, 173]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType RealImagToComplex
Name "Real-Imag to\nComplex"
Ports [2, 1]
Position [425, 253, 455, 282]
}
Block {
BlockType Reference
Name "Sine Wave"
Ports [0, 1]
Position [335, 277, 370, 313]
SourceBlock "dspsrcs4/Sine Wave"
SourceType "Sine Wave"
Amplitude "1"
Frequency "50000"
Phase "0"
SampleMode "Discrete"
OutComplex "Real"
CompMethod "Trigonometric fcn"
TableSize "Speed"
SampleTime "1e-6"
SamplesPerFrame "63"
additionalParams off
allowOverrides on
dataType "double"
wordLen "16"
udDataType "sfix(16)"
fracBitsMode "Best precision"
numFracBits "15"
ResetState "Restart at time zero"
}
Block {
BlockType Reference
Name "Unipolar to\nBipolar\nConverter"
Ports [1, 1]
Position [260, 166, 325, 204]
ShowName off
SourceBlock "commutil2/Unipolar to\nBipolar\nConverter"
SourceType "Unipolar to Bipolar Converter"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
M "2"
polarity "Negative"
dataType "Same as input"
}
Block {
BlockType SubSystem
Name "frequency-syn"
Ports [1, 1]
Position [845, 93, 910, 227]
BackgroundColor "lightBlue"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "frequency-syn"
Location [2, 82, 1270, 753]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [170, 143, 200, 157]
IconDisplay "Port number"
}
Block {
BlockType SubSystem
Name " "
Ports [1, 1]
Position [565, 323, 615, 377]
Orientation "left"
BackgroundColor "lightBlue"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name " "
Location [2, 82, 1270, 753]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [75, 68, 105, 82]
IconDisplay "Port number"
}
Block {
BlockType Sum
Name "Add1"
Ports [2, 1]
Position [400, 77, 430, 108]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain2"
Position [315, 70, 345, 100]
Gain "5"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Integer Delay2"
Ports [1, 1]
Position [400, 123, 430, 157]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "simulink/Discrete/Integer Delay"
SourceType "Integer Delay"
vinit "0"
samptime "-1"
NumDelays "1"
}
Block {
BlockType Reference
Name "Integer Delay3"
Ports [1, 1]
Position [205, 123, 235, 157]
Orientation "left"
NamePlacement "alternate"
ShowName off
SourceBlock "simulink/Discrete/Integer Delay"
SourceType "Integer Delay"
vinit "1"
samptime "-1"
NumDelays "1"
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [210, 67, 240, 98]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Repeat1"
Ports [1, 1]
Position [510, 73, 545, 117]
SourceBlock "dspsigops/Repeat"
SourceType "Repeat"
N "63"
ic "0"
mode "Maintain input frame size"
}
Block {
BlockType Outport
Name "Out1"
Position [610, 88, 640, 102]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Add1"
SrcPort 1
Points [20, 0]
Branch {
Points [0, 45]
DstBlock "Integer Delay2"
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