cdma31.mdl
来自「设计DS-CDMA一种具体的码分导引辅助的信道估计方法」· MDL 代码 · 共 1,582 行 · 第 1/3 页
MDL
1,582 行
DstPort 1
}
Branch {
DstBlock "Repeat1"
DstPort 1
}
}
Line {
SrcBlock "Product2"
SrcPort 1
Points [20, 0]
Branch {
Points [0, 55]
DstBlock "Integer Delay3"
DstPort 1
}
Branch {
DstBlock "Gain2"
DstPort 1
}
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Product2"
DstPort 1
}
Line {
SrcBlock "Integer Delay2"
SrcPort 1
Points [-20, 0; 0, -40]
DstBlock "Add1"
DstPort 2
}
Line {
SrcBlock "Gain2"
SrcPort 1
DstBlock "Add1"
DstPort 1
}
Line {
SrcBlock "Integer Delay3"
SrcPort 1
Points [-15, 0; 0, -50]
DstBlock "Product2"
DstPort 2
}
Line {
SrcBlock "Repeat1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Abs
Name "Abs"
Position [770, 155, 800, 185]
ShowName off
SaturateOnIntegerOverflow off
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Abs
Name "Abs1"
Position [625, 425, 655, 455]
ShowName off
SaturateOnIntegerOverflow off
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [565, 422, 595, 453]
Inputs "-+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Buffer1"
Ports [1, 1]
Position [236, 195, 264, 235]
Orientation "up"
ShowName off
SourceBlock "dspbuff3/Buffer"
SourceType "Buffer"
N "63"
V "0"
ic "0"
}
Block {
BlockType Reference
Name "Compare\nTo Constant"
Ports [1, 1]
Position [841, 240, 879, 280]
Orientation "down"
ShowName off
SourceBlock "simulink/Logic and Bit\nOperations/Compare"
"\nTo Constant"
SourceType "Compare To Constant"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop "<"
const "57"
LogicOutDataTypeMode "boolean"
ZeroCross off
}
Block {
BlockType Constant
Name "Constant"
Position [480, 455, 510, 485]
Value "20000"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion1"
Position [760, 332, 815, 368]
Orientation "left"
NamePlacement "alternate"
ShowName off
OutDataTypeMode "double"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Discrete-Time\nVCO"
Ports [1, 1]
Position [325, 297, 415, 343]
Orientation "left"
NamePlacement "alternate"
ShowName off
FontName "Arial"
SourceBlock "commsynccomp2/Discrete-Time\nVCO"
SourceType "Discrete-Time VCO"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "30000"
Kc "1"
Ph "pi/2"
ts "1e-6"
}
Block {
BlockType Reference
Name "Discrete-Time\nVCO1"
Ports [1, 1]
Position [325, 352, 415, 398]
Orientation "left"
NamePlacement "alternate"
ShowName off
FontName "Arial"
SourceBlock "commsynccomp2/Discrete-Time\nVCO"
SourceType "Discrete-Time VCO"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "30000"
Kc "1"
Ph "0"
ts "1e-6"
}
Block {
BlockType FrameConversion
Name "Frame Conversion"
Position [660, 330, 715, 370]
Orientation "left"
NamePlacement "alternate"
ShowName off
OutFrame "Sample based"
}
Block {
BlockType Gain
Name "Gain1"
Position [690, 425, 720, 455]
Gain "1/50000"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "PN Sequence1"
Ports [0, 1]
Position [335, 195, 410, 235]
ShowName off
SourceBlock "commseqgen2/PN Sequence\nGenerator"
SourceType "PN Sequence Generator"
poly "[6 5 0]"
ini_sta "[0 0 1 0 0 1]"
shift "0"
Ts "1e-6"
frameBased on
sampPerFrame "63"
reset off
outDataType "double"
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [295, 142, 325, 173]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [575, 152, 605, 183]
ShowName off
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType RealImagToComplex
Name "Real-Imag to\nCompex"
Ports [2, 1]
Position [233, 270, 262, 300]
Orientation "up"
ShowName off
}
Block {
BlockType Sum
Name "Sum of\nElements"
Ports [1, 1]
Position [670, 155, 700, 185]
ShowName off
Inputs "+"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Unipolar to\nBipolar\nConverter"
Ports [1, 1]
Position [440, 198, 495, 232]
ShowName off
SourceBlock "commutil2/Unipolar to\nBipolar\nConverter"
SourceType "Unipolar to Bipolar Converter"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
M "2"
polarity "Negative"
dataType "Same as input"
}
Block {
BlockType Outport
Name "Out1"
Position [780, 433, 810, 447]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Gain1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Product2"
SrcPort 1
DstBlock "Sum of\nElements"
DstPort 1
}
Line {
SrcBlock "Abs"
SrcPort 1
Points [55, 0]
DstBlock "Compare\nTo Constant"
DstPort 1
}
Line {
SrcBlock "Compare\nTo Constant"
SrcPort 1
Points [0, 65]
DstBlock "Data Type Conversion1"
DstPort 1
}
Line {
SrcBlock "Data Type Conversion1"
SrcPort 1
DstBlock "Frame Conversion"
DstPort 1
}
Line {
SrcBlock "Buffer1"
SrcPort 1
Points [0, -25]
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Discrete-Time\nVCO1"
SrcPort 1
Points [-80, 0]
DstBlock "Real-Imag to\nCompex"
DstPort 1
}
Line {
SrcBlock "Real-Imag to\nCompex"
SrcPort 1
DstBlock "Buffer1"
DstPort 1
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Product2"
DstPort 1
}
Line {
SrcBlock "Discrete-Time\nVCO"
SrcPort 1
Points [-65, 0]
DstBlock "Real-Imag to\nCompex"
DstPort 2
}
Line {
SrcBlock "PN Sequence1"
SrcPort 1
DstBlock "Unipolar to\nBipolar\nConverter"
DstPort 1
}
Line {
SrcBlock "Unipolar to\nBipolar\nConverter"
SrcPort 1
Points [30, 0; 0, -40]
DstBlock "Product2"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Product1"
DstPort 1
}
Line {
SrcBlock "Sum of\nElements"
SrcPort 1
DstBlock "Abs"
DstPort 1
}
Line {
SrcBlock " "
SrcPort 1
Points [-30, 0]
Branch {
Points [-40, 0]
Branch {
Points [0, -30]
DstBlock "Discrete-Time\nVCO"
DstPort 1
}
Branch {
Points [0, 25]
DstBlock "Discrete-Time\nVCO1"
DstPort 1
}
}
Branch {
Points [0, 80]
DstBlock "Add"
DstPort 1
}
}
Line {
SrcBlock "Frame Conversion"
SrcPort 1
DstBlock " "
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [15, 0; 0, -25]
DstBlock "Add"
DstPort 2
}
Line {
SrcBlock "Add"
SrcPort 1
DstBlock "Abs1"
DstPort 1
}
Line {
SrcBlock "Abs1"
SrcPort 1
DstBlock "Gain1"
DstPort 1
}
}
}
Line {
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
DstBlock "BPSK\nModor\nBaseband"
DstPort 1
}
Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
DstBlock "frequency-syn"
DstPort 1
}
Line {
SrcBlock "PN Sequence1"
SrcPort 1
DstBlock "Unipolar to\nBipolar\nConverter"
DstPort 1
}
Line {
SrcBlock "BPSK\nModor\nBaseband"
SrcPort 1
Points [25, 0; 0, 30]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Unipolar to\nBipolar\nConverter"
SrcPort 1
Points [30, 0; 0, -30]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Multipath Rayleigh\nFading Channel"
SrcPort 1
DstBlock "AWGN\nChannel"
DstPort 1
}
Line {
SrcBlock "frequency-syn"
SrcPort 1
DstBlock "FE"
DstPort 1
}
Line {
SrcBlock "Cos Wave"
SrcPort 1
Points [15, 0; 0, 20]
DstBlock "Real-Imag to\nComplex"
DstPort 1
}
Line {
SrcBlock "Sine Wave"
SrcPort 1
Points [15, 0; 0, -20]
DstBlock "Real-Imag to\nComplex"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Product1"
DstPort 1
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Multipath Rayleigh\nFading Channel"
DstPort 1
}
Line {
SrcBlock "Real-Imag to\nComplex"
SrcPort 1
Points [20, 0; 0, -105]
DstBlock "Product1"
DstPort 2
}
}
}
MatData {
NumRecords 1
DataRecord {
Tag DataTag0
Data " %)30 . > 8 ( 0 % "
"\" $ ! 0 . 2 8 ( ! % \" $ "
"2 0 0 $@ $)E<FYO=6QL:4)I;F%R>4=E;@ "
}
}
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