speaker.vhd

门铃的VHDL程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:36:28 01/10/2009 
-- Design Name: 
-- Module Name:    SPEAKER - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SPEAKER IS
PORT (CLK : IN STD_LOGIC;
     TONE : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
     SPKS : OUT STD_LOGIC );
END;
ARCHITECTURE ONE OF SPEAKER IS
SIGNAL PRECLK,FULLSPKS : STD_LOGIC;
BEGIN
DIVIDECLK : PROCESS(CLK)
VARIABLE COUNT4 : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
PRECLK <= '0';   --将CLK进行16分频
IF COUNT4>11 THEN 
	PRECLK <='1'; 
	COUNT4 := "0000";
ELSIF CLK'EVENT AND CLK = '1' THEN 
	COUNT4 := COUNT4 + 1;
END IF;
END PROCESS;

GENSPKS : PROCESS(PRECLK,TONE) --C11位可预置计数器
VARIABLE COUNT11 : STD_LOGIC_VECTOR (10 DOWNTO 0);
BEGIN
IF PRECLK'EVENT AND PRECLK = '1' THEN
	IF COUNT11 = 16#7FF# THEN 
	COUNT11 := TONE ; FULLSPKS <= '1';
	ELSE COUNT11 := COUNT11 + 1; FULLSPKS <= '0' ; 
	END IF;
END IF;
END PROCESS;

DELAYSPKS : PROCESS(FULLSPKS) --C进行2分频，展宽脉宽，让扬声器有足够功率发声
VARIABLE COUNT2: STD_LOGIC;
BEGIN 
IF FULLSPKS'EVENT AND FULLSPKS = '1' THEN 
	COUNT2 :=NOT COUNT2 ;
	IF COUNT2 = '1' THEN 
		SPKS <= '1';
	ELSE SPKS <='0' ; 
	END IF;
END IF;
END PROCESS;

END;