speaker.syr

门铃的VHDL程序

# IOs                              : 13

Cell Usage :
# BELS                             : 54
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 10
#      LUT2                        : 2
#      LUT3                        : 14
#      LUT3_D                      : 1
#      LUT4                        : 2
#      LUT4_D                      : 1
#      MUXCY                       : 10
#      VCC                         : 1
#      XORCY                       : 10
# FlipFlops/Latches                : 17
#      FD                          : 11
#      FDC                         : 4
#      FDR                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 11
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp20fg676-5 

 Number of Slices:                      18  out of   9280     0%  
 Number of Slice Flip Flops:            17  out of  18560     0%  
 Number of 4 input LUTs:                32  out of  18560     0%  
 Number of IOs:                         13
 Number of bonded IOBs:                 13  out of    404     3%  
 Number of GCLKs:                        1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
PRECLK(PRECLK1:O)                  | NONE(*)(COUNT11_2)     | 12    |
FULLSPKS                           | NONE(COUNT2)           | 1     |
CLK                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
PRECLK(PRECLK1:O)                  | NONE(COUNT4_3)         | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.283ns (Maximum Frequency: 233.468MHz)
   Minimum input arrival time before clock: 2.191ns
   Maximum output required time after clock: 4.061ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'PRECLK'
  Clock period: 4.283ns (frequency: 233.468MHz)
  Total number of paths / destination ports: 198 / 12
-------------------------------------------------------------------------
Delay:               4.283ns (Levels of Logic = 12)
  Source:            COUNT11_1 (FF)
  Destination:       COUNT11_10 (FF)
  Source Clock:      PRECLK rising
  Destination Clock: PRECLK rising

  Data Path: COUNT11_1 to COUNT11_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.419   0.672  COUNT11_1 (COUNT11_1)
     LUT1:I0->O            1   0.351   0.000  Mcount_COUNT11_cy<1>_rt (Mcount_COUNT11_cy<1>_rt)
     MUXCY:S->O            1   0.422   0.000  Mcount_COUNT11_cy<1> (Mcount_COUNT11_cy<1>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<2> (Mcount_COUNT11_cy<2>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<3> (Mcount_COUNT11_cy<3>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<4> (Mcount_COUNT11_cy<4>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<5> (Mcount_COUNT11_cy<5>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<6> (Mcount_COUNT11_cy<6>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<7> (Mcount_COUNT11_cy<7>)
     MUXCY:CI->O           1   0.044   0.000  Mcount_COUNT11_cy<8> (Mcount_COUNT11_cy<8>)
     MUXCY:CI->O           0   0.044   0.000  Mcount_COUNT11_cy<9> (Mcount_COUNT11_cy<9>)
     XORCY:CI->O           1   0.973   0.480  Mcount_COUNT11_xor<10> (Result<10>)
     LUT3:I2->O            1   0.351   0.000  Mcount_COUNT11_eqn_101 (Mcount_COUNT11_eqn_10)
     FD:D                      0.263          COUNT11_10
    ----------------------------------------
    Total                      4.283ns (3.131ns logic, 1.152ns route)
                                       (73.1% logic, 26.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'FULLSPKS'
  Clock period: 1.699ns (frequency: 588.668MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               1.699ns (Levels of Logic = 0)
  Source:            COUNT2 (FF)
  Destination:       COUNT2 (FF)
  Source Clock:      FULLSPKS rising
  Destination Clock: FULLSPKS rising

  Data Path: COUNT2 to COUNT2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.419   0.512  COUNT2 (COUNT2)
     FDR:R                     0.768          COUNT2
    ----------------------------------------
    Total                      1.699ns (1.187ns logic, 0.512ns route)
                                       (69.9% logic, 30.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 2.040ns (frequency: 490.100MHz)
  Total number of paths / destination ports: 10 / 4
-------------------------------------------------------------------------
Delay:               2.040ns (Levels of Logic = 1)
  Source:            COUNT4_0 (FF)
  Destination:       COUNT4_0 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: COUNT4_0 to COUNT4_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.419   0.559  COUNT4_0 (COUNT4_0)
     INV:I->O              1   0.351   0.448  Mcount_COUNT4_xor<0>11_INV_0 (Result<0>)
     FDC:D                     0.263          COUNT4_0
    ----------------------------------------
    Total                      2.040ns (1.033ns logic, 1.007ns route)
                                       (50.6% logic, 49.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'PRECLK'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              2.191ns (Levels of Logic = 2)
  Source:            TONE<0> (PAD)
  Destination:       COUNT11_0 (FF)
  Destination Clock: PRECLK rising

  Data Path: TONE<0> to COUNT11_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.969   0.609  TONE_0_IBUF (TONE_0_IBUF)
     LUT3:I0->O            1   0.351   0.000  Mcount_COUNT11_eqn_01 (Mcount_COUNT11_eqn_0)
     FD:D                      0.263          COUNT11_0
    ----------------------------------------
    Total                      2.191ns (1.583ns logic, 0.609ns route)
                                       (72.2% logic, 27.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'FULLSPKS'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.061ns (Levels of Logic = 1)
  Source:            COUNT2 (FF)
  Destination:       SPKS (PAD)
  Source Clock:      FULLSPKS rising

  Data Path: COUNT2 to SPKS
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.419   0.512  COUNT2 (COUNT2)
     OBUF:I->O                 3.130          SPKS_OBUF (SPKS)
    ----------------------------------------
    Total                      4.061ns (3.549ns logic, 0.512ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
CPU : 8.88 / 9.22 s | Elapsed : 9.00 / 9.00 s
 
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Total memory usage is 194912 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)