coregen.xml

门铃的VHDL程序

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="MUCIC" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
MUCIC YourInstanceName (
    .addr(addr), // Bus [7 : 0] 
    .clk(clk),
    .dout(dout)); // Bus [7 : 0] 

 
		</Template>
		<Template label="MUCIC_ROM" treetype="template">
		</Template>
		<Template label="MUSIC_ROM" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
MUSIC_ROM YourInstanceName (
    .addr(addr), // Bus [7 : 0] 
    .clk(clk),
    .dout(dout)); // Bus [7 : 0] 

 
		</Template>
		<Template label="DD" treetype="template">
		</Template>
		<Template label="MUSIC" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
MUSIC YourInstanceName (
    .addr(addr), // Bus [7 : 0] 
    .clk(clk),
    .dout(dout)); // Bus [7 : 0] 

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="MUCIC" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component MUCIC
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0));
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : MUCIC
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            dout =&gt; dout);
 
		</Template>
		<Template label="MUCIC_ROM" treetype="template">
		</Template>
		<Template label="MUSIC_ROM" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component MUSIC_ROM
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0));
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : MUSIC_ROM
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            dout =&gt; dout);
 
		</Template>
		<Template label="DD" treetype="template">
		</Template>
		<Template label="MUSIC" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component MUSIC
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0));
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : MUSIC
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            dout =&gt; dout);
 
		</Template>
	</Folder>
</RootFolder>