tone.syr

门铃的VHDL程序

Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.24 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.24 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: TONE.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "TONE.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "TONE"
Output Format                      : NGC
Target Device                      : xc2vp20-5-fg676

---- Source Options
Top Module Name                    : TONE
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Convert Tristates To Logic         : Yes
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : TONE.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "G:/ISE9.1/menling/tune.vhd" in Library work.
Entity <tone> compiled.
Entity <TONE> (Architecture <ONE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <TONE> in library <work> (architecture <ONE>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <TONE> in library <work> (Architecture <ONE>).
Entity <TONE> analyzed. Unit <TONE> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <TONE>.
    Related source file is "G:/ISE9.1/menling/tune.vhd".
WARNING:Xst:737 - Found 11-bit latch for signal <TONE>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 4-bit latch for signal <CODE>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <HIGH1>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
Unit <TONE> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Latches                                              : 3
 1-bit latch                                           : 1
 11-bit latch                                          : 1
 4-bit latch                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2vp20.nph' in environment E:\ISE9.1.
WARNING:Xst:1710 - FF/Latch  <0> (without init value) has a constant value of 0 in block <3>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Latches                                              : 3
 1-bit latch                                           : 1
 11-bit latch                                          : 1
 4-bit latch                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <CODE_3> (without init value) has a constant value of 0 in block <TONE>.

Optimizing unit <TONE> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block TONE, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : TONE.ngr
Top Level Output File Name         : TONE
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 20

Cell Usage :
# BELS                             : 17
#      GND                         : 1
#      LUT4                        : 16
# FlipFlops/Latches                : 15
#      LD                          : 15
# IO Buffers                       : 20
#      IBUF                        : 4
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp20fg676-5 

 Number of Slices:                       9  out of   9280     0%  
 Number of 4 input LUTs:                16  out of  18560     0%  
 Number of IOs:                         20
 Number of bonded IOBs:                 20  out of    404     4%  
    IOB Flip Flops:                     15

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
TONE_or0000(TONE_or00001:O)        | NONE(*)(TONE_7)        | 15    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: 2.595ns
   Maximum output required time after clock: 4.214ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'TONE_or0000'
  Total number of paths / destination ports: 60 / 15
-------------------------------------------------------------------------
Offset:              2.595ns (Levels of Logic = 2)
  Source:            INDEX<3> (PAD)
  Destination:       HIGH1 (LATCH)
  Destination Clock: TONE_or0000 falling

  Data Path: INDEX<3> to HIGH1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            16   0.969   1.012  INDEX_3_IBUF (INDEX_3_IBUF)
     LUT4:I0->O            1   0.351   0.000  HIGH1_or00011 (HIGH1_or0001)
     LD:D                      0.263          HIGH1
    ----------------------------------------
    Total                      2.595ns (1.583ns logic, 1.012ns route)
                                       (61.0% logic, 39.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'TONE_or0000'
  Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Offset:              4.214ns (Levels of Logic = 1)
  Source:            HIGH1 (LATCH)
  Destination:       HIGH1 (PAD)
  Source Clock:      TONE_or0000 falling

  Data Path: HIGH1 to HIGH1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.636   0.448  HIGH1 (HIGH1_OBUF)
     OBUF:I->O                 3.130          HIGH1_OBUF (HIGH1)
    ----------------------------------------
    Total                      4.214ns (3.766ns logic, 0.448ns route)
                                       (89.4% logic, 10.6% route)

=========================================================================
CPU : 8.30 / 8.56 s | Elapsed : 8.00 / 8.00 s
 
--> 

Total memory usage is 193888 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    4 (   0 filtered)