top.syr

门铃的VHDL程序

Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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--> Reading design: TOP.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "TOP.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "TOP"
Output Format                      : NGC
Target Device                      : xc2vp20-5-fg676

---- Source Options
Top Module Name                    : TOP
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Convert Tristates To Logic         : Yes
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : TOP.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "G:/ISE9.1/menling/MUSIC.vhd" in Library work.
Architecture music_a of Entity music is up to date.
Compiling vhdl file "G:/ISE9.1/menling/NoteTabs.vhd" in Library work.
Architecture one of Entity notetabs is up to date.
Compiling vhdl file "G:/ISE9.1/menling/tune.vhd" in Library work.
Architecture one of Entity tone is up to date.
Compiling vhdl file "G:/ISE9.1/menling/SPEAKER.vhd" in Library work.
Architecture one of Entity speaker is up to date.
Compiling vhdl file "G:/ISE9.1/menling/TOP .vhd" in Library work.
Entity <top> compiled.
ERROR:HDLParsers:164 - "G:/ISE9.1/menling/TOP .vhd" Line 38. parse error, unexpected END, expecting IDENTIFIER
--> 

Total memory usage is 112040 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)