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<title>VHDL LRM - Introduction</title>
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<h1>IEEE Standard VHDL Language Reference Manual<br>
(IEEE Std. 1076-1993)</h1>
<p>Sponsors
<h2>Design Automation Standards Committee<code><br>
</code>of the<code><br>
</code>IEEE Computer Society </h2>
<p>and
<h2>Automatic Test Program Generation Subcommittee<code><br>
</code>of <code><br>
</code>IEEE Standards Coordinating Committee 20</h2>
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Approved September 15, 1993<br>
<b>IEEE Standards Board</b><br>
Approved April 14, 1994<br>
<b>American National Standards Institute</b><p>
<b>Abstract:</b> This standard defines the VHSIC Hardware Description Language (VHDL). VHDL is a formal notation
intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human
readable, it supports the development, verification, synthesis , and testing of hardware designs; the communication of
hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audience are the
implementers of tools supporting the language and the advanced users of the language.<p>
<b>Keywords:</b> Computer, computer languages, electronic systems, hardware, hardware design, VHDL<p>
<p>The Institute of Electrical and Electronics Engineers, Inc.<code><br>
</code>345 East 47th Street, New York, NY 10017-2394, USA
<p>Copyright © 1994 by<code>
</code>The Institute of Electrical and Electronics Engineers, Inc.<code><br>
</code>All rights reserved. Published 1994<code>
</code>Printed in the United States of America<br>
<p>ISBN 1-55937-376-8
<p><i>No part of this publication may be reproduced in any form,in an electronic retrieval system or otherwise,without
the prior written permission of the publisher.</i><br>
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<h1><a name="./1076_intro.html">Introduction</a></h1>
<p>(This introduction is not a part of IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual.)
<p>The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware.
<p>This document specifies IEEE Std 1076-1993, which is a revision of IEEE Std 1076-1987. The VHDL Analysis and Standardization Group (VASG) of the Computer Society of the IEEE started the development of IEEE Std 1076-1993 in June 1990. The VASG commissioned a Standardization Steering Committee to drive the standardization effort. The Steering Committee created standardization chapters in North America, Europe, and Asia-Pacific; administered the standardization guidelines of the IEEE; and staffed the volunteer positions in the various standardization chapters.
<p>New capabilities in this version of the language include groups, shared variables, hierarchical pathnames, and a facility to include foreign models in a VHDL description. Some of the existing capabilities were extended or modified to facilitate initial and incremental creation of a design hierarchy. New shift/rotate operators were added to the language. The delay model of the language was modified to support pulse rejection. The syntactic consistency of the language was enhanced. Finally, resolutions of ambiguities and inconsistencies addressed by the Issue Screening and Analysis Committee (ISAC) of the VASG were incorporated into this revision of the language.
<p>The VHDL 92 standardization effort consisted of five major phases: definition of VHDL 92 requirements, language design, language documentation, design validation, and balloting. The following working documents were developed during each phase of the standardization effort:
<pre> Requirements Definition: VHDL 92 Requirements
VHDL 92 Design Objectives Document
Language Design: Language Change Specifications
Language Documentation: Draft and Final Language Reference Manuals
Design Validation: Validation Reports
Ballot Response Document: Balloting
</pre>
<p>Numerous volunteers in North America, Europe, and Asia-Pacific contributed to development of VHDL 92. The Standardization Steering Committee consisted of the following:
<pre> Moe Shahdad Steering Committee Chair
Stan Krolikoski VASG Chair
Victor Berman North-American Chapter Chair
Jean Mermet European Chapter Chair
Kazuyuki Hirakawa Asia-Pacific Chapter Chair
Jacques Rouillard
Ron Waxman
John Hillawi
Andreas Hohl
</pre>
<p>The following volunteers led the various working groups of the standardization effort:
<pre> Requirements Definition Jacques Rouillard
Language Design Doug Dunlop
Language Documentation Paul Menchini
Design Validation Alex Zamfirescu
Ballot Comment Resolution Clive Charlwood
</pre>
<p>In addition, the following volunteers in the North America, European, and Asia-Pacific standardization chapters contributed to the VHDL 92 standardization effort by participating in the requirements gathering, requirements analysis, design review, documentation review, design validation, and balloting:
<p>
<pre> Mart Altm鋏 Eric Gutt Zainalabedin Navabi
Stephen A. Bailey Andrew Guyler Wolfgang Nebel
Daniel Barclay William A. Hanna Mary Lynne Nielsen
Jean-Michel Berg⌨️ 快捷键说明
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