test_mult.vhd

用impulse c编写的18x18位的乘法器。

-----------------------------------------------------------------------------
-- test_mult.vhd: simple test bench
--
-- This test bench instantiates and tests the process generated by
-- CoDeveloper. 
--
-- Copyright 2004, Impulse Accelerated Technologies.  All rights reserved.
-----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use work.config.all;

entity test_top is
end test_top;

architecture behavior of test_top is
    signal reset, sclk, clk : std_ulogic;
    signal p_producer_process_Operand_en : std_ulogic;
    signal p_producer_process_Operand_eos : std_ulogic;
    signal p_producer_process_Operand_data : std_ulogic_vector (17 downto 0);
    signal p_producer_process_Operand_rdy : std_ulogic;
    signal p_consumer_process_Result_en : std_ulogic;
    signal p_consumer_process_Result_data : std_ulogic_vector (35 downto 0);
    signal p_consumer_process_Result_eos : std_ulogic;
    signal p_consumer_process_Result_rdy : std_ulogic;
    constant PERIOD: time := 10 ns;
component mult_arch is
  port (
    reset, sclk, clk : in std_ulogic;
    p_producer_process_Operand_en : in std_ulogic;
    p_producer_process_Operand_eos : in std_ulogic;
    p_producer_process_Operand_data : in std_ulogic_vector (17 downto 0);
    p_producer_process_Operand_rdy : out std_ulogic;
    p_consumer_process_Result_en : in std_ulogic;
    p_consumer_process_Result_data : out std_ulogic_vector (36 downto 0);
    p_consumer_process_Result_eos : out std_ulogic;
    p_consumer_process_Result_rdy : out std_ulogic);
end component mult_arch;
begin
	reset_stimulus: process
	begin
		reset <= '1'; wait for PERIOD;
		reset <= '0'; wait;
	end process;

	sclk_stimulus: process
	begin
		sclk <= '0'; wait for PERIOD/2;
		sclk <= '1'; wait for PERIOD/2;
	end process;

	clk_stimulus: process
	begin
		clk <= '0'; wait for PERIOD/2;
		clk <= '1'; wait for PERIOD/2;
	end process;

	stimulus: process
		variable k : integer;
	begin
		p_producer_process_Operand_eos <= '0';
		p_producer_process_Operand_en <= '0';
		p_producer_process_Operand_data <= "000000000000000000";
		wait for PERIOD*2;

		-- Output the Operand values
		
		k := 0;
		while true loop
			p_producer_process_Operand_en <= '0';
			if (p_producer_process_Operand_rdy = '1') then
				p_producer_process_Operand_data <= testval_table(k);
				p_producer_process_Operand_en <= '1';
				k := k+1;
			end if;
			wait until rising_edge(clk);
			if k=testval_count then
				exit;
			end if;
		end loop;

	end process stimulus;

	results: process
	begin
		p_consumer_process_Result_en <= '1';
		while (p_consumer_process_Result_eos = '0') loop
			-- results will appear on p_consumer_process_Operand_data
			wait until rising_edge(clk);
		end loop;
		wait;
	end process;

	-- Instantiate the design under test
	DUT: entity work.mult_arch
		port map (
			reset, sclk, clk,
			p_producer_process_Operand_en,
			p_producer_process_Operand_eos,
			p_producer_process_Operand_data,
			p_producer_process_Operand_rdy,
			p_consumer_process_Result_en,
			p_consumer_process_Result_data,
			p_consumer_process_Result_eos,
			p_consumer_process_Result_rdy
		);
end behavior;