rtc_tb.v

Verilog code for RTC

module rtc_tb;
    reg [4:0]hrs;
    reg [5:0]mts,secs;
    reg clk,reset;
    reg [8:0]days;
    wire [5:0]i_secs,i_mts;
    wire [4:0]i_hrs;
    wire [8:0]i_days;
    rtc r1(.secs(secs),.mts(mts),.hrs(hrs),.i_hrs(i_hrs),.i_mts(i_mts),.i_secs(i_secs),.clk(clk),.reset(reset),.days(days),.i_days(i_days));
    initial
    begin
        clk=0;
        reset=0;
        $display("Time");
        $monitor("hrs=%d,mts=%d,secs=%d,days=%d",hrs,mts,secs,days);
        hrs=1;mts=1;secs=1;days=1;
        #1 reset=1;
    end
    always
      begin
      #1; clk = ~clk;
      end
  endmodule