rtc.v

Verilog code for RTC

module rtc(hrs,mts,secs,days,i_days,i_hrs,i_mts,i_secs,clk,reset);   
   input hrs,mts,secs,clk,reset,days;
   output i_hrs,i_mts,i_secs,i_days;
   wire clk;
   wire reset;
   wire [4:0]hrs;
   wire [5:0]mins;
   wire [5:0]secs;
   wire [8:0]days;
   reg [5:0]i_secs;
   reg [5:0]i_mts;
   reg [4:0]i_hrs;
   reg [8:0]i_days;
   
    
 
//Real-Time Clock Implementation
  always @(posedge clk or negedge reset)
	begin
       if(reset==0)
       begin
       i_hrs = hrs;
       i_mts = mts;
       i_secs = secs;
			end
			else  begin
  				   i_secs <= i_secs+1;
 					if(i_secs==6'd60)  begin  i_mts <= i_mts+1;  i_secs <= 6'd0;  end
					if(i_mts==6'd60) begin  i_hrs <= i_hrs+1;  i_mts <= 6'd0;  end
                              if(i_hrs==5'd24) begin i_days <= i_days+1; i_hrs <= 5'd0; end
                              
       			
       		
			end
       
	end
   
endmodule