dram.v

来自「RISC（reduced instruction setcomputer」· Verilog 代码 · 共 26 行

module dram (
   clk,
   address,
   we,
   din,
   dout
);

input		clk;
input [6:0]	address;
input		we;
input [7:0]	din;
output [7:0]	dout;

parameter word_depth = 70; 

reg [7:0]	mem[0:word_depth-1];

assign dout = mem[address];

// write

always @(posedge clk)
   if (we) mem[address] <= din;

endmodule