a.tan.qmsg

异步置位复位D触发器

{ "Info" "ITDB_TSU_RESULT" "q~reg0 d clk 3.022 ns register " "Info: tsu for register \"q~reg0\" (data pin = \"d\", clock pin = \"clk\") is 3.022 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.409 ns + Longest pin register " "Info: + Longest pin to register delay is 5.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns d 1 PIN PIN_G18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G18; Fanout = 1; PIN Node = 'd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { d } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.636 ns) + CELL(0.539 ns) 5.409 ns q~reg0 2 REG LC_X1_Y27_N4 1 " "Info: 2: + IC(3.636 ns) + CELL(0.539 ns) = 5.409 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.175 ns" { d q~reg0 } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 32.78 % ) " "Info: Total cell delay = 1.773 ns ( 32.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.636 ns ( 67.22 % ) " "Info: Total interconnect delay = 3.636 ns ( 67.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.409 ns" { d q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.409 ns" { d d~out0 q~reg0 } { 0.000ns 0.000ns 3.636ns } { 0.000ns 1.234ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.397 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns clk 1 CLK PIN_J17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.621 ns) + CELL(0.542 ns) 2.397 ns q~reg0 2 REG LC_X1_Y27_N4 1 " "Info: 2: + IC(0.621 ns) + CELL(0.542 ns) = 2.397 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.163 ns" { clk q~reg0 } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 74.09 % ) " "Info: Total cell delay = 1.776 ns ( 74.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.621 ns ( 25.91 % ) " "Info: Total interconnect delay = 0.621 ns ( 25.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { clk q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.397 ns" { clk clk~out0 q~reg0 } { 0.000ns 0.000ns 0.621ns } { 0.000ns 1.234ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.409 ns" { d q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.409 ns" { d d~out0 q~reg0 } { 0.000ns 0.000ns 3.636ns } { 0.000ns 1.234ns 0.539ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { clk q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.397 ns" { clk clk~out0 q~reg0 } { 0.000ns 0.000ns 0.621ns } { 0.000ns 1.234ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q q~reg0 5.724 ns register " "Info: tco from clock \"clk\" to destination pin \"q\" through register \"q~reg0\" is 5.724 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.397 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns clk 1 CLK PIN_J17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.621 ns) + CELL(0.542 ns) 2.397 ns q~reg0 2 REG LC_X1_Y27_N4 1 " "Info: 2: + IC(0.621 ns) + CELL(0.542 ns) = 2.397 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.163 ns" { clk q~reg0 } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 74.09 % ) " "Info: Total cell delay = 1.776 ns ( 74.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.621 ns ( 25.91 % ) " "Info: Total interconnect delay = 0.621 ns ( 25.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { clk q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.397 ns" { clk clk~out0 q~reg0 } { 0.000ns 0.000ns 0.621ns } { 0.000ns 1.234ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.171 ns + Longest register pin " "Info: + Longest register to pin delay is 3.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X1_Y27_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { q~reg0 } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(2.376 ns) 3.171 ns q 2 PIN PIN_G20 0 " "Info: 2: + IC(0.795 ns) + CELL(2.376 ns) = 3.171 ns; Loc. = PIN_G20; Fanout = 0; PIN Node = 'q'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.171 ns" { q~reg0 q } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 74.93 % ) " "Info: Total cell delay = 2.376 ns ( 74.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.795 ns ( 25.07 % ) " "Info: Total interconnect delay = 0.795 ns ( 25.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.171 ns" { q~reg0 q } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.171 ns" { q~reg0 q } { 0.000ns 0.795ns } { 0.000ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { clk q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.397 ns" { clk clk~out0 q~reg0 } { 0.000ns 0.000ns 0.621ns } { 0.000ns 1.234ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.171 ns" { q~reg0 q } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.171 ns" { q~reg0 q } { 0.000ns 0.795ns } { 0.000ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q~reg0 d clk -2.912 ns register " "Info: th for register \"q~reg0\" (data pin = \"d\", clock pin = \"clk\") is -2.912 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.397 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns clk 1 CLK PIN_J17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.621 ns) + CELL(0.542 ns) 2.397 ns q~reg0 2 REG LC_X1_Y27_N4 1 " "Info: 2: + IC(0.621 ns) + CELL(0.542 ns) = 2.397 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.163 ns" { clk q~reg0 } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 74.09 % ) " "Info: Total cell delay = 1.776 ns ( 74.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.621 ns ( 25.91 % ) " "Info: Total interconnect delay = 0.621 ns ( 25.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { clk q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.397 ns" { clk clk~out0 q~reg0 } { 0.000ns 0.000ns 0.621ns } { 0.000ns 1.234ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.409 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns d 1 PIN PIN_G18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G18; Fanout = 1; PIN Node = 'd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { d } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.636 ns) + CELL(0.539 ns) 5.409 ns q~reg0 2 REG LC_X1_Y27_N4 1 " "Info: 2: + IC(3.636 ns) + CELL(0.539 ns) = 5.409 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.175 ns" { d q~reg0 } "NODE_NAME" } } { "a.vhd" "" { Text "C:/Users/minghui/Documents/编程/异步置位复位D触发器/a.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 32.78 % ) " "Info: Total cell delay = 1.773 ns ( 32.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.636 ns ( 67.22 % ) " "Info: Total interconnect delay = 3.636 ns ( 67.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.409 ns" { d q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.409 ns" { d d~out0 q~reg0 } { 0.000ns 0.000ns 3.636ns } { 0.000ns 1.234ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.397 ns" { clk q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.397 ns" { clk clk~out0 q~reg0 } { 0.000ns 0.000ns 0.621ns } { 0.000ns 1.234ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.409 ns" { d q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.409 ns" { d d~out0 q~reg0 } { 0.000ns 0.000ns 3.636ns } { 0.000ns 1.234ns 0.539ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 24 08:47:55 2009 " "Info: Processing ended: Tue Feb 24 08:47:55 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}