📄 a.tan.rpt
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Timing Analyzer report for a
Tue Feb 24 08:47:55 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.022 ns ; d ; q~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 5.724 ns ; q~reg0 ; q ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.912 ns ; d ; q~reg0 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 3.022 ns ; d ; q~reg0 ; clk ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 5.724 ns ; q~reg0 ; q ; clk ;
+-------+--------------+------------+--------+----+------------+
+--------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A ; None ; -2.912 ns ; d ; q~reg0 ; clk ;
+---------------+-------------+-----------+------+--------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Feb 24 08:47:55 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off a -c a --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "q~reg0" (data pin = "d", clock pin = "clk") is 3.022 ns
Info: + Longest pin to register delay is 5.409 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G18; Fanout = 1; PIN Node = 'd'
Info: 2: + IC(3.636 ns) + CELL(0.539 ns) = 5.409 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.773 ns ( 32.78 % )
Info: Total interconnect delay = 3.636 ns ( 67.22 % )
Info: + Micro setup delay of destination is 0.010 ns
Info: - Shortest clock path from clock "clk" to destination register is 2.397 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.621 ns) + CELL(0.542 ns) = 2.397 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.776 ns ( 74.09 % )
Info: Total interconnect delay = 0.621 ns ( 25.91 % )
Info: tco from clock "clk" to destination pin "q" through register "q~reg0" is 5.724 ns
Info: + Longest clock path from clock "clk" to source register is 2.397 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.621 ns) + CELL(0.542 ns) = 2.397 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.776 ns ( 74.09 % )
Info: Total interconnect delay = 0.621 ns ( 25.91 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.171 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'
Info: 2: + IC(0.795 ns) + CELL(2.376 ns) = 3.171 ns; Loc. = PIN_G20; Fanout = 0; PIN Node = 'q'
Info: Total cell delay = 2.376 ns ( 74.93 % )
Info: Total interconnect delay = 0.795 ns ( 25.07 % )
Info: th for register "q~reg0" (data pin = "d", clock pin = "clk") is -2.912 ns
Info: + Longest clock path from clock "clk" to destination register is 2.397 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.621 ns) + CELL(0.542 ns) = 2.397 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.776 ns ( 74.09 % )
Info: Total interconnect delay = 0.621 ns ( 25.91 % )
Info: + Micro hold delay of destination is 0.100 ns
Info: - Shortest pin to register delay is 5.409 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G18; Fanout = 1; PIN Node = 'd'
Info: 2: + IC(3.636 ns) + CELL(0.539 ns) = 5.409 ns; Loc. = LC_X1_Y27_N4; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.773 ns ( 32.78 % )
Info: Total interconnect delay = 3.636 ns ( 67.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Tue Feb 24 08:47:55 2009
Info: Elapsed time: 00:00:01
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