a.vhd

异步置位复位D触发器

--异步置位/复位D触发器
library ieee;
use ieee.std_logic_1164.all;
entity a is
   port(clk,d,clr,pset:in std_logic;
        q:out std_logic);
end a;
architecture rtl of a is
begin
   process(clk,pset,clr)
   begin
      if(pset='0') then
         q<='1';
      elsif(clr='0') then
         q<='0';
      elsif(clk'event and clk='1') then
         q<=d;
      end if;
   end process;
end rtl;