binary_to_decima.vhd

8位全加器的VHDL描述

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity binary_to_decima is
port( SW : in std_logic_vector(3 downto 0);
	  HEX0 : out std_logic_vector(0 to 6);
	  HEX1 : out std_logic_vector(0 to 6));
end entity;
architecture one of binary_to_decima is
component comparator
	port ( M : in std_logic_vector(3 downto 0);
		   Z : out bit);
end component;
component circle_A
	port( a : in std_logic_vector(2 downto 0);
		  b : in bit;
	      M : out std_logic_vector(2 downto 0));
end component;
component circle_B
	port( b : in bit;
	      M : out std_logic_vector(0 to 6));
end component;
component char_7seg
	port( M : in std_logic_vector(3 downto 0);
	  D : out std_logic_vector(0 to 6));
end component;
signal D : bit;
signal T : std_logic_vector(2 downto 0);
signal W : std_logic_vector(3 downto 0);
begin
	u1 : comparator port map(SW,D);
	u2 : circle_A port map(SW(2 downto 0),D,T);
	u3 : circle_B port map(D,HEX1);
	process(D,T)
	begin
		--W <=('1'&T) when D='0'; --else ('0'&T);
		if D='0' then W <=(SW(3)&T);else W <=('0'&T);
	end if;

	end process;
	
	u4:char_7seg port map(W,HEX0);

end architecture;