divp5.vhd

fpga上实现的最小是0.5分频的任意分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity divp5 is
generic(n : Positive := 4);
port ( clkin : in std_logic;
         rst : in std_logic;
	  preset : in std_logic_vector(n-1 downto 0);
	  clkout : out std_logic);
end divp5;
ARCHITECTURE adiv of divp5 is
	SIGNAL  clk,div : std_logic;
	SIGNAL  clkp5,clk2 : std_logic;
	SIGNAL  count,count1,count2,cnt,cnt1 : std_logic_vector(n-1 downto 0);
BEGIN
------------------------------------------------0.5倍分频	
clk<=clkin xor div;
	Process (clk)
	begin
	if (clk 'event and clk='1') then
		if (count="0000") then
			count<=cnt-1;
			clkp5<='1';
		else 
			count<=count-1;
			clkp5<='0';
		end if;
	end if;
	end Process;
	
	Process (clkp5,rst)
	begin
	if (rst='1') then
		div<='0';
	elsif (clkp5 'event and clkp5='1') then
		div<=not div;
	end if;
	end Process;
-----------------------------------------------------n的整数倍分频	
	count1<=TO_STDLOGICVECTOR(TO_BITVECTOR(cnt1) srl 1);
	Process
	begin
	wait until rising_edge(clkin);
		if count2>=(cnt1-1) then
			count2<="0000";
		else 
			count2<=count2+1;
		end if;
		if count2>=count1 then
			clk2<='1';
		else
			clk2<='0';
		end if;
	end process;
--------------------------------------------------------输出选择	
	Process (preset)
	begin
		case preset is  --//分频数为(preset+2)/2
			when "0000" => 
			when "0001" => 
				cnt<="0010";
			when "0010" => 
				cnt1<="0010";	
			when "0011" => 
				cnt<="0011";
			when "0100" => 
				cnt1<="0011";	
			when "0101" =>
				cnt<="0100";
			when "0110" => 
				cnt1<="0100";	
			when "0111" => 
				cnt<="0101";
			when "1000" => 
				cnt1<="0101";
			when "1001" => 
				cnt<="0110";
			when "1010" => 
				cnt1<="0110";	
			when "1011" => 
				cnt<="0111";
			when "1100" => 
				cnt1<="0111";	
			when "1101" =>
				cnt<="1000";
			when "1110" => 
				cnt1<="1000";	
			when "1111" => 
				cnt<="1001";
		end case;
	end Process;
	
	clkout<= clkin when rst='0' and preset="0000" else
			 clkp5 when rst='0' and preset="0001" else
			 clk2  when rst='0' and preset="0010" else
			 clkp5 when rst='0' and preset="0011" else
			 clk2  when rst='0' and preset="0100" else
			 clkp5 when rst='0' and preset="0101" else
			 clk2  when rst='0' and preset="0110" else
			 clkp5 when rst='0' and preset="0111" else
			 clk2  when rst='0' and preset="0100" else
			 clkp5 when rst='0' and preset="1001" else
			 clk2  when rst='0' and preset="1010" else
			 clkp5 when rst='0' and preset="1011" else
			 clk2  when rst='0' and preset="1100" else
			 clkp5 when rst='0' and preset="1101" else
			 clk2  when rst='0' and preset="1110" else
			 clkp5 when rst='0' and preset="1111" else
			 '0';
		
END adiv;