📄 ring.txt
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity migajace_diody is
Port(CLK : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (7 downto 0));
end migajace_diody;
architecture Behavioral of migajace_diody is
begin
process(CLK,R)
variable cnt: integer range 0 to 50000000:=0;
variable predkosc: integer range 0 to 7:=0;
begin
if R='1' then Q<="00000001";
elsif rising_edge(CLK) then
cnt:=cnt+1;
if cnt=50000000 then cnt:=0;
end if;
if predkosc=0 then
if cnt=49999999 then
Q<=Q(6 downto 0)&Q(7);
if Q="10000000" then predkosc:=1; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=1 then
if cnt=24999999 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=2; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=2 then
if cnt=12499999 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=3; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=3 then
if cnt=6249999 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=4; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=4 then
if cnt=3124999 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=5; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=5 then
if cnt=1562499 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=6; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=6 then
if cnt=781249 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=7; cnt:=0; Q<="00000001";
end if;
end if;
elsif predkosc=7 then
if cnt=390624 then
Q<=Q(6 downto 0)&Q(7);
cnt:=0;
if Q="10000000" then predkosc:=0; cnt:=0; Q<="00000001";
end if;
end if;
end if;
end if;
if R=
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