pong_top.sch

Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "spartan3"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        BEGIN SIGNAL seg_a
            BEGIN ATTR LOC "e14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_b
            BEGIN ATTR LOC "g13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_c
            BEGIN ATTR LOC "n15"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_d
            BEGIN ATTR LOC "p15"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_e
            BEGIN ATTR LOC "r16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_f
            BEGIN ATTR LOC "f13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_g
            BEGIN ATTR LOC "n16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL seg_dp
            BEGIN ATTR LOC "p16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(0)
            BEGIN ATTR LOC "d14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(1)
            BEGIN ATTR LOC "g14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(2)
            BEGIN ATTR LOC "f14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL an(3)
            BEGIN ATTR LOC "e13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(2)
            BEGIN ATTR LOC "l12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(4)
            BEGIN ATTR LOC "p13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(5)
            BEGIN ATTR LOC "n12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(6)
            BEGIN ATTR LOC "p12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(7)
            BEGIN ATTR LOC "p11"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_red
            BEGIN ATTR LOC "r12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_green
            BEGIN ATTR LOC "t12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_blue
            BEGIN ATTR LOC "r11"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_hs
            BEGIN ATTR LOC "r9"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL vga_vs
            BEGIN ATTR LOC "t10"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ps2c
            BEGIN ATTR LOC "m16"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL clk_ic4
            BEGIN ATTR LOC "t9"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL clk_ic8
            BEGIN ATTR LOC "d9"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(0)
            BEGIN ATTR LOC "f12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(1)
            BEGIN ATTR LOC "g12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(2)
            BEGIN ATTR LOC "h14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(3)
            BEGIN ATTR LOC "h13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(4)
            BEGIN ATTR LOC "j14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(5)
            BEGIN ATTR LOC "j13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(6)
            BEGIN ATTR LOC "k14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL sw(7)
            BEGIN ATTR LOC "k13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL rxd
            BEGIN ATTR LOC "t13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL txd
            BEGIN ATTR LOC "r13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ps2d
            BEGIN ATTR LOC "m15"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL btn(0)
            BEGIN ATTR LOC "m13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL btn(1)
            BEGIN ATTR LOC "m14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL btn(2)
            BEGIN ATTR LOC "l13"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        SIGNAL sw(7:0)
        BEGIN SIGNAL ld(0)
            BEGIN ATTR LOC "k12"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(1)
            BEGIN ATTR LOC "p14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        BEGIN SIGNAL ld(3)
            BEGIN ATTR LOC "n14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        SIGNAL an(3:0)
        SIGNAL ld(7:0)
        SIGNAL XLXN_31(1:0)
        SIGNAL hsync
        SIGNAL vsync
        SIGNAL lf_dir(1:0)
        SIGNAL rt_dir(1:0)
        SIGNAL serve
        SIGNAL seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g,seg_dp
        SIGNAL btn(3:0)
        BEGIN SIGNAL btn(3)
            BEGIN ATTR LOC "l14"
                VERILOG all:0 wsynth:1
                VHDL all:0 wa:1 wd:1
            END ATTR
        END SIGNAL
        PORT Output seg_a
        PORT Output seg_b
        PORT Output seg_c
        PORT Output seg_d
        PORT Output seg_e
        PORT Output seg_f
        PORT Output seg_g
        PORT Output seg_dp
        PORT Output an(0)
        PORT Output an(1)
        PORT Output an(2)
        PORT Output an(3)
        PORT Output ld(2)
        PORT Output ld(4)
        PORT Output ld(5)
        PORT Output ld(6)
        PORT Output ld(7)
        PORT Output vga_red
        PORT Output vga_green
        PORT Output vga_blue
        PORT Output vga_hs
        PORT Output vga_vs
        PORT Input ps2c
        PORT Input clk_ic4
        PORT Input clk_ic8
        PORT Input sw(0)
        PORT Input sw(1)
        PORT Input sw(2)
        PORT Input sw(3)
        PORT Input sw(4)
        PORT Input sw(5)
        PORT Input sw(6)
        PORT Input sw(7)
        PORT Input rxd
        PORT Output txd
        PORT Input ps2d
        PORT Input btn(0)
        PORT Input btn(1)
        PORT Input btn(2)
        PORT Output ld(0)
        PORT Output ld(1)
        PORT Output ld(3)
        PORT Output hsync
        PORT Input btn(3)
        BEGIN BLOCKDEF vga_int
            TIMESTAMP 2004 9 13 18 46 46
            RECTANGLE N 64 -320 352 0 
            LINE N 64 -288 0 -288 
            RECTANGLE N 0 -60 64 -36 
            LINE N 64 -48 0 -48 
            LINE N 352 -288 416 -288 
            LINE N 352 -224 416 -224 
            LINE N 352 -160 416 -160 
            LINE N 352 -96 416 -96 
            LINE N 352 -32 416 -32 
            LINE N 64 -208 0 -208 
            LINE N 64 -128 0 -128 
        END BLOCKDEF
        BEGIN BLOCKDEF cntrl
            TIMESTAMP 2004 10 27 16 54 36
            LINE N 64 -288 0 -288 
            LINE N 64 -224 0 -224 
            LINE N 64 -160 0 -160 
            LINE N 320 -208 384 -208 
            LINE N 320 -128 384 -128 
            RECTANGLE N 320 -60 384 -36 
            LINE N 320 -48 384 -48 
            RECTANGLE N 64 -320 320 0 
            LINE N 64 -96 0 -96 
            RECTANGLE N 0 -108 64 -84 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
        END BLOCKDEF
        BEGIN BLOCKDEF read_ps2
            TIMESTAMP 2004 10 26 14 41 1
            LINE N 64 -224 0 -224 
            LINE N 64 -160 0 -160 
            LINE N 64 -96 0 -96 
            LINE N 64 -32 0 -32 
            LINE N 320 -160 384 -160 
            LINE N 320 -96 384 -96 
            RECTANGLE N 320 -108 384 -84 
            RECTANGLE N 320 -172 384 -148 
            RECTANGLE N 64 -256 320 12 
            LINE N 320 -224 384 -224 
            RECTANGLE N 320 -44 384 -20 
            LINE N 320 -32 384 -32 
        END BLOCKDEF
        BEGIN BLOCKDEF game_title
            TIMESTAMP 2004 9 27 16 48 41
            RECTANGLE N 64 -128 320 0 
            LINE N 64 -96 0 -96 
            LINE N 320 -96 384 -96 
            RECTANGLE N 320 -108 384 -84 
            LINE N 320 -32 384 -32 
            RECTANGLE N 320 -44 384 -20 
        END BLOCKDEF
        BEGIN BLOCK read_ps2_inst read_ps2
            PIN Clk clk_ic4
            PIN PS2_Clk ps2c
            PIN PS2_Data ps2d
            PIN Reset btn(3)
            PIN left_dir(1:0) lf_dir(1:0)
            PIN right_dir(1:0) rt_dir(1:0)
            PIN serve serve
            PIN ps2_code(7:0) ld(7:0)
        END BLOCK
        BEGIN BLOCK cntrl_inst cntrl
            PIN CLK clk_ic4
            PIN RESET btn(3)
            PIN SERVE serve
            PIN HSYNCH hsync
            PIN VSYNCH vsync
            PIN COLOR(1:0) XLXN_31(1:0)
            PIN left_dir(1:0) lf_dir(1:0)