pong.tbw

Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of

version 3
e:\data\examples\pong\pong_top.vf
pong_top
VERILOG
VERILOG
pong.xwv
Clocked
-
-
100000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk_ic4
10000000
10000000
2000000
1000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
an
clk_ic4
btn
clk_ic4
clk_ic8
clk_ic4
hsync
clk_ic4
ld
clk_ic4
ps2c
clk_ic4
ps2d
clk_ic4
rxd
clk_ic4
seg_a
clk_ic4
seg_b
clk_ic4
seg_c
clk_ic4
seg_d
clk_ic4
seg_dp
clk_ic4
seg_e
clk_ic4
seg_f
clk_ic4
seg_g
clk_ic4
sw
clk_ic4
txd
clk_ic4
vga_blue
clk_ic4
vga_green
clk_ic4
vga_hs
clk_ic4
vga_red
clk_ic4
vga_vs
clk_ic4
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
an_DIFF
hsync_DIFF
ld_DIFF
seg_a_DIFF
seg_b_DIFF
seg_c_DIFF
seg_d_DIFF
seg_dp_DIFF
seg_e_DIFF
seg_f_DIFF
seg_g_DIFF
txd_DIFF
vga_blue_DIFF
vga_green_DIFF
vga_hs_DIFF
vga_red_DIFF
vga_vs_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk_ic4
clk_ic8
ps2c
ps2d
rxd
btn
sw
hsync
seg_a
seg_b
seg_c
seg_d
seg_dp
seg_e
seg_f
seg_g
txd
vga_blue
vga_green
vga_hs
vga_red
vga_vs
an
ld
SIGNAL_ORDER_END
-X-X-X-