basegate.v

来自「采用Altera公司的CycloneII芯片EP2C8的一些程序代码。」· Verilog 代码 · 共 31 行

module BaseGate(
					Sw_n,
					Led_En_n,
					Led,
					
					Buzz,
					Sev_Seg_Led_Sel_n
				);

input [3:0] Sw_n;

output Led_En_n;
output [7:0] Led;

output Buzz;
output [3:0] Sev_Seg_Led_Sel_n;

	assign 
		Led_En_n = 1'd0;

	assign 
		Led[0] = ~Sw_n[1] | ~Sw_n[0],
		Led[7:1] = 7'd0;

	assign
		Buzz = 1'd0;  //禁止蜂鸣器工作
		
	assign
		Sev_Seg_Led_Sel_n = 4'b1111;  //禁止七段数码管显示
	
endmodule