freedev_aic23.v

在开发FPGA上比较有用

module freedev_aic23(clk,rst_n,cs_n,rd_n,wr_n,addr,rdata,wdata,
                    lrcin,din,lrcout,dout,bclk);

// parameter
	
input clk;		// master clk
input rst_n;	// reset
input cs_n;		// chip select
input rd_n;		// read signal
input wr_n;		// write signal
input [2:0]addr;// address
output [15:0]rdata;	// out data
input  [15:0]wdata;	// in  data

reg [15:0] rdata;

input  lrcin;    // aic master mode,from AIC23 to fpga
output din;      // to DAC
input  lrcout;   // aic master mode,from AIC23 TO fpga
input  dout;     // from ADC
input  bclk;     // bclk from AIC23

reg din;

//
// variable declarations
//

// registers
reg [15:0] register[3:0];	// segment data

// generate write signals
wire wacc = ~cs_n & ~wr_n;

// generate read signals
wire racc = ~cs_n & ~rd_n;
reg [7:0] trans_data;

// clk时钟域
// generate registers
always @(posedge clk or negedge rst_n)
	if (!rst_n)
	begin
	   register[0] <= #1 16'h0000;
	   register[1] <= #1 16'h0000;
	   register[2] <= #1 16'h0000;
		register[3] <= #1 16'h0000;
	end
	else
	    if ( wacc )
		begin
	      case ( addr ) // synopsis parallel_case
			3'b000 : register[0] <= #1 wdata;
			3'b001 : register[1] <= #1 wdata;
			3'b010 : register[2] <= #1 wdata;
			3'b011 : register[3] <= #1 wdata;	         
			default: ;
	      endcase
		end

	always @(posedge clk)
	begin
	if( racc )
	  case (addr) // synopsis parallel_case
	    3'b000: rdata <= #1 register[0];
	    3'b001: rdata <= #1 register[1];
	    3'b010: rdata <= #1 register[2];
	    3'b011: rdata <= #1 register[3]; 
	    3'b100: rdata <= #1 8'h4;  	// reserved
	    3'b101: rdata <= #1 8'h5;	// reserved
	    3'b110: rdata <= #1 8'h6;	// reserved
	    3'b111: rdata <= #1 8'h7;   // reserved
	  endcase
	end
	
	//bclk时钟域
	reg s_lrcin,d_lrcin;    //lrcin同步和延时
	reg s_lrcout,d_lrcout;  //lrcout同步和延时
   
   always @(posedge bclk)
   begin
       d_lrcin <= s_lrcin;
       s_lrcin <= lrcin;
       d_lrcout <= s_lrcout;
       s_lrcout <= lrcout;
   end
   
   wire in_flag,out_flag;   //AIC23 DSP MODE

   assign in_flag = ~d_lrcout & s_lrcout;
   assign out_flag= ~d_lrcin  & s_lrcin;

   reg    [31:0]recv;       // recv data from aic23 adc
   reg    [31:0]recved;     // recved data
   reg    [4:0]recv_count;  // recv counter
   reg    [31:0]send;       // send data to dac
   reg    [31:0]sended;     // sended data
   reg    [4:0]send_count;  // send counter
      
   reg    [1:0]recv_state;  // recv state
   reg    [1:0]send_state;  // send state
   
   // state machine
	parameter IDLE  = 2'b00;
	parameter START = 2'b01;
	parameter STOP  = 2'b10;
	parameter HOLD  = 2'b11;
	
   always @(posedge bclk)
   if(~rst_n)
	begin
	    recv_state <= IDLE;
	end else
   begin
      if(lrcin)
        begin
           recved <= #1 recv;
           recv <= #1 32'h0;
           recv_count <= #1 5'h0;
           recv_state <= #1 START;      
        end
       else if(recv_state == START)
       begin
          recv <= #1 {recv[30:0],dout};
          recv_count <= recv_count + 5'h1;
          if( recv_count == 5'b11111)
          begin
              recv_state <= #1 STOP;
          end    
       end
   end 
   
   always @(negedge bclk)
   if(~rst_n)
	begin
	    send_state <= IDLE;
	end else 
   begin  
       if(out_flag)
       begin
		  din <= #1 recved[31]; 
          send <= #1 {recved[30:0],1'b0};
          send_count <= #1 5'h1;  
          send_state <= #1 START; 
       end
       else if(send_state == START)
       begin
          din <= #1 send[31];
          send <= #1 {send[30:0],1'b0};
          send_count <= send_count + 5'h1;
          if( send_count == 5'b11111)
          begin
              send_state <= #1 STOP;
          end    
       end
   end
   
//assign din = dout;   
endmodule