aic23_testbench.v

在开发FPGA上比较有用

`timescale 1ns/1ns
`define clk_cyle 20

module test_sig;

reg clk,reset_n;
reg [15:0]data;
reg [15:0]prescale;
reg start;
wire busy;
wire s_clk;
wire s_dat; 
reg cs_n;
reg rd_n;
reg wr_n;
reg [2:0]addr;
wire [7:0]rdata;
reg [7:0]wdata;
 

always #`clk_cyle clk=~clk; //create clk

initial
begin
    clk=0;
    /* segment test */
    reset_n=1;
    #20 reset_n=0;
    #100 reset_n=1;
    
    /*  shift_data test */
    /*
    prescale=4;
    start=0;
    data=16'b1111_0111_1010_1010;
    reset_n=1;
    #20 reset_n=0;
    #100 reset_n=1;
    #20 start=1;
    #100 start=0;
    */
    
    #100000 $stop;
    
end
wire out_clk;
 
sigment the_sigment(clk,reset_n,cs_n,rd_n,wr_n,addr,rdata,wdata,s_clk,s_dat,out_clk);    
//shift_bit the_shift_bit(clk,reset_n,prescale,data,start,busy,s_clk,s_dat);
   
endmodule