ceshi.v

实现交通灯

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:28:19 02/20/2009
// Design Name:   test
// Module Name:   D:/ise_book/traffic/ceshi.v
// Project Name:  traffic
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: test
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module ceshi_v;

	// Inputs
	reg clk;
	reg rst;
	reg ucar;
	reg lcar;

	// Outputs
	wire [5:0] lights;

	// Instantiate the Unit Under Test (UUT)
	test uut (
		.clk(clk), 
		.rst(rst), 
		.ucar(ucar), 
		.lcar(lcar), 
		.lights(lights)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		ucar = 0;
		lcar = 0;

		// Wait 100 ns for global reset to finish
		#10 rst=1;
		#10 rst=0;
      #10 lcar=1; 
		#10 ucar=1;		
		// Add stimulus here
	end
	
//	initial begin
		
	always
		#5 clk=~clk;
		
      
endmodule