test.v

实现交通灯

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:59:58 02/20/2009 
// Design Name: 
// Module Name:    test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test(clk, rst, ucar, lcar, lights);
    input clk;
    input rst;
    input ucar;
    input lcar;
    output [5:0] lights;
	 
	 reg [5:0] lights;
	 reg [2:0] current_state,next_state;
	 reg time1able,flag1;
	 reg [7:0] count1;
	 
	 parameter up_green  = 3'b000;
    parameter up_green_wait  = 3'b001;
    parameter up_yellow  = 3'b010;
    parameter left_green  = 3'b011;
    parameter left_green_wait  = 3'b100;
    parameter left_yellow  = 3'b101;

	// parameter greentime=,yellowtime=2;
	 initial
		begin
			lights<=6'b001001;
			current_state<=up_green;
			next_state=up_green;
			count1=0;time1able=0;flag1=0;
		end
		
	 always @(posedge clk)
		if(rst)
		   begin 
		   current_state<=up_green;
	//	   count1=0;time1able=0;flag1=0;
         end
		else
			current_state<=next_state;
			
	  always @(posedge clk)
		begin
			 if(rst)
			 begin
				count1=0;time1able=0;flag1=0;
			end
		    if(flag1==1)
		    begin		        
		        if(count1==2)
		           time1able=1;
		        else count1=count1+1;
		    end
			
			case(current_state)
				up_green:
					begin
					   if(flag1==0) flag1=1;
					   if(time1able==1)
					   begin
						   next_state=up_green_wait;
						   time1able=0;
						   flag1=0;
						   count1=0;
						end
				   end
				up_green_wait:
					begin
						if(lcar==1) next_state=up_yellow;
						else next_state=up_green;
					end
				up_yellow:
					begin
					   if(flag1==0) flag1=1;
					   if(time1able==1)
					   begin
						   next_state=left_green;
						   time1able=0;
						   flag1=0;
						   count1=0;
				      end
					end
				left_green:
					begin
					   if(flag1==0) flag1=1;
					   if(time1able==1)
					   begin
						   next_state=left_green_wait;
						   time1able=0;
						   flag1=0;
						   count1=0;
						end
				   end
				left_green_wait:
					begin
						if(ucar==1) next_state=left_yellow;
						else next_state=left_green;
					end
				left_yellow:
					begin
					   if(flag1==0) flag1=1;
					   if(time1able==1)
					   begin
						   next_state=up_green;
						   time1able=0;
						   flag1=0;
						   count1=0;
						end
				   end
				default:
					next_state=up_green;
			endcase
		end		
			
		always@(posedge clk)
			case(current_state)
				up_green:
					begin
						lights<=6'b100001;
					end
				up_yellow:
					begin
						lights<=6'b010001;
					end
				left_green:
					begin
						lights<=6'b001100;
					end
				left_yellow:
					begin
						lights<=6'b001010;
					end
//				default:
//						lights<=6'b001001;
			endcase
			
	//	task delay(input[3:0] timedelay)	;
		//	repeat (timedelay) @ (posedge clk);
//		endtask
		
//		always@(posedge clk)
//		begin
//		    if(flag1==1)
//		    begin		        
//		        if(count1==2)
//		           time1able=1;
//		        else count1=count1+1;
//		    end
		//end
		
endmodule