digital_watch_core.v

it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin

//--------------------------------------------------------------------------------------------------
//    Project      : Digital Watch Core
//    File         : digital_watch_core.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing (FPGA based Digital Design using Verilog HDL) Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements ....
// 
//    Modification History:
//---------------------------------------------------------------------------------------------------
//    Date                       By               Version                Change Description
//---------------------------------------------------------------------------------------------------
//    15 April, 2008       Irfan & Nauman          0.1                     1st Version
//---------------------------------------------------------------------------------------------------

module digital_watch_core(// Inputs
                          clk,
                          rst_n,
                          enable,
                          // Ouputs
                          sec_digits,
                          min_digits,
                          hrs_digits
                         );
//---- Port Declarations ----
input        clk;
input        rst_n;
input        enable;

output [7:0] sec_digits;
output [7:0] min_digits;
output [7:0] hrs_digits;

//-- Intermediate signal declarations --
wire       ovflw_1sec, ovflw_10sec;
wire       ovflw_1min, ovflw_10min;
wire       ovflw_1hrs, ovflw_10hrs;

wire [3:0] sec1_val, sec10_val;
wire [3:0] min1_val, min10_val;
wire [3:0] hrs1_val, hrs10_val;

reg        soft_reset;

wire       reset_sig;
wire [7:0] sec_digits;
wire [7:0] min_digits;
wire [7:0] hrs_digits;


assign reset_sig = rst_n & soft_reset;

assign sec_digits = {sec10_val, sec1_val};
assign min_digits = {min10_val, min1_val};
assign hrs_digits = {hrs10_val, hrs1_val};


always @(posedge clk or negedge rst_n)
begin
   if(~rst_n)
      soft_reset <= 1'b1;
   else if(hrs10_val == 4'd2 && hrs1_val == 4'd4) // Active Low Reset Signal...
      soft_reset <= 1'b0;
   else
      soft_reset <= 1'b1;
end

// For Simulation use #(32,40) ===== For Synthesis use #(32,40000000)
cnter_enb_ovf #(32,40) clkdiv_cnter(// Inputs
                                          .clk          (clk),
                                          .rst_n        (reset_sig),
                                          .enable       (enable),
                                          // Outputs
                                          .overflow     (ovflw_1sec),
                                          .cnt_val      ()
                                         );

cnter_enb_ovf #(4,10) sec1_cnter(// Inputs
                                 .clk          (clk),
                                 .rst_n        (reset_sig),
                                 .enable       (ovflw_1sec),
                                 // Outputs
                                 .overflow     (ovflw_10sec),
                                 .cnt_val      (sec1_val)
                                );

cnter_enb_ovf #(4,6) sec10_cnter(// Inputs
                                 .clk          (clk),
                                 .rst_n        (reset_sig),
                                 .enable       (ovflw_10sec),
                                 // Outputs
                                 .overflow     (ovflw_1min),
                                 .cnt_val      (sec10_val)
                                );

cnter_enb_ovf #(4,10) min1_cnter(// Inputs
                                 .clk          (clk),
                                 .rst_n        (reset_sig),
                                 .enable       (ovflw_1min),
                                 // Outputs
                                 .overflow     (ovflw_10min),
                                 .cnt_val      (min1_val)
                                );

cnter_enb_ovf #(4,6) min10_cnter(// Inputs
                                 .clk          (clk),
                                 .rst_n        (reset_sig),
                                 .enable       (ovflw_10min),
                                 // Outputs
                                 .overflow     (ovflw_1hrs),
                                 .cnt_val      (min10_val)
                                );

cnter_enb_ovf #(4,10) hrs1_cnter(// Inputs
                                 .clk          (clk),
                                 .rst_n        (reset_sig),
                                 .enable       (ovflw_1hrs),
                                 // Outputs
                                 .overflow     (ovflw_10hrs),
                                 .cnt_val      (hrs1_val)
                                );

cnter_enb_ovf #(4,6) hrs10_cnter(// Inputs
                                 .clk          (clk),
                                 .rst_n        (reset_sig),
                                 .enable       (ovflw_10hrs),
                                 // Outputs
                                 .overflow     (),
                                 .cnt_val      (hrs10_val)
                                );
endmodule