jtdkz.vhd

这是一个vhdl的例子

library ieee;
use ieee.std_logic_1164.all;
entity jtdkz is
port (clk,sensm,sensf:in std_logic;
rm,ym,gm,rf,yf,gf:out std_logic);
end jtdkz;
architecture arc of jtdkz is
type state_type is (a,b,c,d);

signal state:state_type;

begin

cnt:process(clk)
variable s:integer range 0 to 29;
variable nclr,en:bit;

begin
if(clk'event and clk='1') then
if nclr='0' then s:=0;
elsif en='0' then s:=s;
else s:=s+1;
end if;

case state is
when a=>rm<='0';ym<='0';gm<='1';
rf<='1';yf<='0';gf<='0';
if(sensf and sensm)='1' then
if s=29 then
state<=b;nclr:='0';en:='0';
else
state<=a;nclr:='1';en:='1';
end if;
elsif (sensf and(not sensm))='1' then
state<=b;nclr:='0';en:='0';
else
state<=a;nclr:='1';en:='1';
end if;
when b=>rm<='0';ym<='1';gm<='0';
rf<='1';yf<='0';gf<='0';
if s=3 then
state<=c;nclr:='0';en:='0';
else
state<=b;nclr:='1';en:='1';
end if;
when c=>rm<='1';ym<='0';gm<='0';
rf<='0';yf<='0';gf<='1';
if(sensf and sensm)='1' then
if s=29 then
state<=d;nclr:='0';en:='0';
else
state<=c;nclr:='1';en:='1';
end if;
elsif sensf='0' then
state<=d;nclr:='0';en:='0';
else
state<=c;nclr:='1';en:='1';
end if;
when d=>rm<='1';ym<='0';gm<='0';
rf<='0';yf<='1';gf<='0';
if s=3 then
state<=a;nclr:='0';en:='0';
else
state<=d;nclr:='1';en:='1';
end if;
end case;
end if;
end process cnt;
end arc;