📄 jtdkz.rpt
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14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\zy\jtdkz.rpt
jtdkz
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 14 clk
Device-Specific Information: e:\zy\jtdkz.rpt
jtdkz
** EQUATIONS **
clk : INPUT;
sensf : INPUT;
sensm : INPUT;
-- Node name is ':24' = 'en'
-- Equation name is 'en', location is LC8_B21, type is buried.
en = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC3_B21
# _LC4_B21 & !state0 & !state1;
-- Node name is 'gf'
-- Equation name is 'gf', type is output
gf = _LC4_B16;
-- Node name is 'gm'
-- Equation name is 'gm', type is output
gm = _LC8_B16;
-- Node name is 'rf'
-- Equation name is 'rf', type is output
rf = _LC2_B16;
-- Node name is 'rm'
-- Equation name is 'rm', type is output
rm = _LC3_B16;
-- Node name is ':17' = 'state0'
-- Equation name is 'state0', location is LC1_B21, type is buried.
state0 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC6_B21
# _LC7_B21 & !state0 & !state1;
-- Node name is ':16' = 'state1'
-- Equation name is 'state1', location is LC7_B16, type is buried.
state1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_B24 & state0 & !state1
# !state0 & state1
# !_LC2_B24 & state1;
-- Node name is ':22' = 's0'
-- Equation name is 's0', location is LC5_B13, type is buried.
s0 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = en & !s0;
-- Node name is ':21' = 's1'
-- Equation name is 's1', location is LC2_B13, type is buried.
s1 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = en & s0 & !s1
# en & !s0 & s1;
-- Node name is ':20' = 's2'
-- Equation name is 's2', location is LC4_B13, type is buried.
s2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = en & !s0 & s2
# en & !s1 & s2
# en & s0 & s1 & !s2;
-- Node name is ':19' = 's3'
-- Equation name is 's3', location is LC4_B24, type is buried.
s3 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = en & !_LC1_B13 & s3
# en & _LC1_B13 & !s3;
-- Node name is ':18' = 's4'
-- Equation name is 's4', location is LC3_B24, type is buried.
s4 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = en & _LC8_B24;
-- Node name is 'yf'
-- Equation name is 'yf', type is output
yf = _LC6_B16;
-- Node name is 'ym'
-- Equation name is 'ym', type is output
ym = _LC1_B16;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ009);
_EQ009 = s0 & s1 & s2;
-- Node name is ':4'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = DFFE( state1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':6'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = state0 & !state1;
-- Node name is ':8'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !state0 & !state1;
-- Node name is ':10'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = DFFE(!state1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':12'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = state0 & state1;
-- Node name is ':14'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !state0 & state1;
-- Node name is ':122'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = LCELL( _EQ014);
_EQ014 = !s3 & s4
# !_LC1_B13 & s4
# en & _LC1_B13 & s3 & !s4
# !en & s4;
-- Node name is '~196~1'
-- Equation name is '~196~1', location is LC6_B13, type is buried.
-- synthesized logic cell
_LC6_B13 = LCELL( _EQ015);
_EQ015 = !en & s1
# en & s0 & !s1
# !s0 & s1
# !s0 & !s2
# !s1 & !s2
# !en & !s2
# s1 & s2;
-- Node name is '~196~2'
-- Equation name is '~196~2', location is LC8_B13, type is buried.
-- synthesized logic cell
_LC8_B13 = LCELL( _EQ016);
_EQ016 = !en
# !_LC8_B24
# s0
# _LC6_B13;
-- Node name is ':196'
-- Equation name is '_LC1_B24', type is buried
!_LC1_B24 = _LC1_B24~NOT;
_LC1_B24~NOT = LCELL( _EQ017);
_EQ017 = _LC8_B13
# !_LC1_B13 & !s3
# en & _LC1_B13 & s3
# !en & !s3;
-- Node name is ':274'
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = LCELL( _EQ018);
_EQ018 = sensf & !sensm
# _LC1_B24 & sensf;
-- Node name is ':292'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ019);
_EQ019 = !_LC1_B24 & sensm
# !sensf;
-- Node name is '~312~1'
-- Equation name is '~312~1', location is LC7_B13, type is buried.
-- synthesized logic cell
_LC7_B13 = LCELL( _EQ020);
_EQ020 = !en
# !s0 & !s1
# s0 & s1
# !s0 & s2
# !s1 & s2;
-- Node name is '~312~2'
-- Equation name is '~312~2', location is LC3_B13, type is buried.
-- synthesized logic cell
_LC3_B13 = LCELL( _EQ021);
_EQ021 = !en & !s0
# en & s0
# _LC8_B24
# _LC7_B13;
-- Node name is ':312'
-- Equation name is '_LC2_B24', type is buried
!_LC2_B24 = _LC2_B24~NOT;
_LC2_B24~NOT = LCELL( _EQ022);
_EQ022 = !_LC1_B13 & s3
# en & _LC1_B13 & !s3
# !en & s3
# _LC3_B13;
-- Node name is ':464'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ023);
_EQ023 = _LC1_B24 & sensm
# !sensf;
-- Node name is ':482'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ024);
_EQ024 = !_LC1_B24 & sensf
# sensf & !sensm;
-- Node name is ':664'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ025);
_EQ025 = _LC5_B21 & !state0 & state1
# !_LC2_B24 & state0;
-- Node name is ':688'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ026);
_EQ026 = _LC2_B21 & !state0 & state1
# !_LC2_B24 & state0;
Project Information e:\zy\jtdkz.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,137K
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