disturb.tan.qmsg

适用于初学者的一个m序列扰、解码器

{ "Info" "ITDB_TH_RESULT" "Dif:D5\|tp input CLK -1.948 ns register " "Info: th for register \"Dif:D5\|tp\" (data pin = \"input\", clock pin = \"CLK\") is -1.948 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.986 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 232 -8 160 248 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.542 ns) 2.986 ns Dif:D5\|tp 2 REG LC_X52_Y10_N7 1 " "Info: 2: + IC(1.616 ns) + CELL(0.542 ns) = 2.986 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.158 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.88 % ) " "Info: Total cell delay = 1.370 ns ( 45.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 54.12 % ) " "Info: Total interconnect delay = 1.616 ns ( 54.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.034 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns input 1 PIN PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_P2; Fanout = 2; PIN Node = 'input'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { input } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 128 -8 160 144 "input" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.163 ns) + CELL(0.280 ns) 4.677 ns inst~13 2 COMB LC_X52_Y10_N6 2 " "Info: 2: + IC(3.163 ns) + CELL(0.280 ns) = 4.677 ns; Loc. = LC_X52_Y10_N6; Fanout = 2; COMB Node = 'inst~13'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.443 ns" { input inst~13 } "NODE_NAME" } } { "Disturb.bdf" "" { Schematic "C:/Documents and Settings/doctor shi/桌面/Disturb/Disturb.bdf" { { 104 168 232 152 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 5.034 ns Dif:D5\|tp 3 REG LC_X52_Y10_N7 1 " "Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 5.034 ns; Loc. = LC_X52_Y10_N7; Fanout = 1; REG Node = 'Dif:D5\|tp'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.357 ns" { inst~13 Dif:D5|tp } "NODE_NAME" } } { "Dif.vhd" "" { Text "C:/Documents and Settings/doctor shi/桌面/Disturb/Dif.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns ( 34.51 % ) " "Info: Total cell delay = 1.737 ns ( 34.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.297 ns ( 65.49 % ) " "Info: Total interconnect delay = 3.297 ns ( 65.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.034 ns" { input inst~13 Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.034 ns" { input input~out0 inst~13 Dif:D5|tp } { 0.000ns 0.000ns 3.163ns 0.134ns } { 0.000ns 1.234ns 0.280ns 0.223ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.986 ns" { CLK Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.986 ns" { CLK CLK~out0 Dif:D5|tp } { 0.000ns 0.000ns 1.616ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.034 ns" { input inst~13 Dif:D5|tp } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.034 ns" { input input~out0 inst~13 Dif:D5|tp } { 0.000ns 0.000ns 3.163ns 0.134ns } { 0.000ns 1.234ns 0.280ns 0.223ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 17 19:52:55 2008 " "Info: Processing ended: Wed Dec 17 19:52:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}